User's Manual
Table Of Contents
- General Description
- Features
- System Applications
- Block Diagram
- Pin Assignments
- Pin Descriptions
- CPU Access to Endpoint Data
- USB Request
- Get Descriptor-Device
- Get Descriptor-Device Qualifier (High Speed)
- Get Descriptor-Configuration
- Get Descriptor-String Index 0
- Get Descriptor-String Index 1
- Get Descriptor-String Index 2
- Get Descriptor-String Index 3
- Get Descriptor-String Index 4
- Get Descriptor-String Index 5
- Get Descriptor-Other Speed Configuration
- Set Address
- Set Interface 0
- Set Feature Device
- Clear Feature Device
- Set Config 0
- Set Config 1
- EEPROM (93C46 or 93C56) Contents
- USB Packet Buffering
- Functional Description
- Application Diagram
- Electrical Characteristics
- Mechanical Dimensions
- Ordering Information
RTL8187L
Datasheet
Wireless LAN Network Interface Controller 3 Track ID JATR-1076-21 Rev. 1.2
4. Block Diagram
MAC/BBP
Interface
Interrupt
Control
Logic
FIFO
Transmit/
Receive
Logic
Interface
RTS, CTS,
ACK Frame
Generator
FIFO
Control
Logic
Frame Type
Discriminator
Power and TX/RX Timing Control Logic
SIE + Register
Frame Length
Register
EEPROM
Interface
LED Driver
Scrambler
TXI
MAC
BBP, TX Section
CCA/
NAV
From BBP
WEP/
TKIP/
AES
Engine
Checksum
Logic
Serial
Control
Radio and
Synthesizer
Control
Coding
Digital
Filter
TXQ
TXDET
TXAGC
TX AGC
Control
Descrambler
RXI
MAC/BBP
Interface
Decoding
ADC
RXQ
DAC
RSSI
RXAGC
RX AGC
Control
ADC
ADC
Clear Channel
Assessment/
Signal Quality
Antenna
Diversity
Control
TX State
Machine
Register
From
MAC
RX State
Machine
Register
From
MAC
To MAC
D+
D-
BBP, RX Section
MAC/BBP
Interface
DAC
ADC
DAC
DAC
ANTSELB
ANTSEL
Figure 1. Block Diagram