User's Manual

RTL8822CE
Datasheet
Single-Chip 802.11 ac/a/b/g/n 2T2R WLAN Controller
with PCI-E Interface
15
Track ID: Rev. 0.1
7. Interface Timing Specification
7.1. PCIe Bus during Power On Sequence
3.3V
CLKREQ#
PERST#
REFCLK
USB D+
USB D-
T
on
SE0 Reset
Card
Detection
T
PVPGL
T
PERST#-CLK
BT_DIS#
Tattach
T
k-state
WL_DIS#
Figure 3. RTL8822CE PCIe and USB Bus Power On Sequence
T
on
: The main power ramp up duration
T
PVPGL
: Power valid to PERST# input inactive
T
PERST#-CLK
: Reference clock stable before PERST# inactive
T
attach
: The interval to turn on BT after PERST# de-asserted
T
k-state
: the duration from resister attached to USB host starting card detection procedure
Symbol
Unit
Min
Typical
Max
T
on
ms
0.5
1.5
5
T
PVPGL
ms
Implementation
specific;recommended 50ms
--
T
PERST#-CLK
us
100
--
T
attach
ms
0.5
2
5
T
k-state
ms
50
250
--
Table 16. The typical timing range