User's Manual

PRELIMINARY

PRELIMINARY PRELIMINARY

PRELIMINARY –

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Service

ServiceService

Service Manual

Manual Manual

Manual

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Fig.3. AF Amplifier and squelch

6） Receiving signaling

QT/DQT

300 Hz and higher audio frequencies of the output signal from IF IC

are cut by a low-pass filter (IC301). The resulting signal enters the

microprocessor (IC403). IC403 determines whether the QT or DQT

matches the preset value, and controls the MUTE and AFCO and the

speaker output sounds according to the squelch results.

3. PLL frequency synthesizer

The PLL circuit generates the first local oscillator signal for reception and

the RF signal for transmission.

2） PLL

The frequency step of the PLL circuit is 5 or 6.25KHz. A 12.8MHz

reference oscillator signal is divided at IC1 by a fixed counter to

produce the 5 or 6.25KHz reference frequency. The voltage controlled

oscillator (VCO) output signal is buffer amplified by Q6, then divided in

IC1 by a dual-module programmable counter. The divided signal is

compared in phase with the 5 or 6.25KHz reference signal in the phase

comparator in IC1. The output signal from the phase comparator is

filtered through a low-pass filter and passed to the VCO to control the

oscillator frequency. (See Fig. 4)

2) VCO