User's Manual

RYZ012 Multi-Standard Wireless Communication Module for Bluetooth 5 Low Energy and 802.15.4
R15UH0002EU0103 Rev.1.03 Page 104 of 206
Apr.21.21
11. PWM
The RYZ012 has six Pulse-Width-Modulation (PWM) channels. Each PWM has separate direct (non-inverted) outputs named PWMx. In
addition, for channels 0-2 and 4, inverted outputs named PWMxN are available.
The PWM clock derives from the system clock. PWM:CLKDIV serves as frequency divider for the PWM clock, such that F
PWM
=F
SYS
/(
PWM:CLKDIV+1).
Each PWM channel has an independent counter which counts from 0 to PWM:TMAXx. As long as the counter value is below PWM:TCMPx, a
high level output is generated; afterwards, a low level output is generated on the corresponding direct pin until the counter reaches
PWM:TMAXx. The polarity of the generated signal can be inverted through register PWM:POL independently for each channel. In addition, the
polarity of the direct output and the inverted output can be controlled through registers PWM:DPOL and PWM:IPOL, respectively.
Figure 18. PWM, PWM Output Generation
The individual PWM channels are enabled through register
PWM:EN. When the PWM is disabled, the corresponding output turns low
immediately. An interruption will be generated at the end of each signal frame if enabled through bit 2 to 7 of PWM:MASK0.
11.1 PWM Modes
PWM0 supports three modes, including Continuous, Counting, and IR Mode. PWM1–PWM5 only support Continuous Mode. The register
PWM:MODE serves to select PWM0 mode.
11.1.1 Continuous Mode
Continuous Mode is supported by all PWM channels. In this mode, the PWM continuously sends out signal frames. The frequency and duty
cycle of the generated waveform can be changed freely through registers
PWM:TMAXx and PWM:TCMPx. Changes to these registers will
take effect in the next signal frame.