User's Manual

RYZ012 Multi-Standard Wireless Communication Module for Bluetooth 5 Low Energy and 802.15.4
R15UH0002EU0103 Rev.1.03 Page 105 of 206
Apr.21.21
After completion of a signal frame, the corresponding PWM cycle done interrupt flag PWM:INT0:FRx is set. If the interrupt is enabled in register
PWM:MASK0, an interrupt request is sent to the interrupt controller. The user needs to write 1b'1 to the flag bit to manually clear it.
11.1.2 Counting Mode
Only PWM0 supports Counting mode.
PWM:MODE:MODE should be set as 4b'0001 to select PWM0 counting mode. In this mode, PWM0
sends out specified number of signal frames which are defined as a pulse group. The number is configured through register PWM:PNUM0.
After completion of each signal frame, the cycle done interrupt flag (PWM:INT0:FR0) is set. If the interrupt is enabled in register
PWM:MASK0:FR0, an interrupt request is sent to the interrupt controller. The interrupt flag is cleared by writing 1b'1 to it.
After completion of the pulse group, PWM0 is disabled automatically, and the interrupt flag PWM:INT0:CNT0 is set. If the interrupt is enabled
in register
PWM:MASK0:CNT0, an interrupt request is sent to the interrupt controller. The interrupt flag is cleared by writing 1b'1 to it.
Figure 19. Counting Mode
Counting mode also serves to stop IR mode gracefully. See
IR Mode for details.
11.1.3 IR Mode
Only PWM0 supports IR mode.
PWM:MODE:MODE should be set as 4b'0011 to select PWM0 IR mode. IR Mode is similar to Counting Mode
with the difference that pulse groups are sent continuously.
During IR mode, PWM0 output waveform can be changed freely through
PWM:TCMP0, PWM:TMAX0, and PWM:PNUM0. The new
configuration of these registers takes effect in the next pulse group.
To stop IR mode and complete the current pulse group, the user can switch PWM0 from IR mode to Counting mode so that PWM0 stops after
the current pulse group is finished. If PWM0 is disabled directly through
PWM:EN:CH0EN, PWM0 output turns Low immediately despite of the
current pulse group. After completion of each frame and pulse group, the corresponding interrupt flags PWM:INT0:FR0 and PWM:INT0:CNT0
are set. If the corresponding interrupt is enabled in register
PWM:MASK0, an interrupt request is sent to the interrupt controller. The interrupt
flags are cleared by writing 1b'1 to them.
Figure 20. IR Mode