User's Manual

RYZ012 Multi-Standard Wireless Communication Module for Bluetooth 5 Low Energy and 802.15.4
R15UH0002EU0103 Rev.1.03 Page 162 of 206
Apr.21.21
14. SAR-ADC
The RYZ012 integrates one SAR ADC module, which can be used to sample analog input signals such as battery voltage, temperature sensor,
mono or stereo audio signals. The SAR ADC is disabled by default. To power on the ADC, the analog register SCTL:APCTRL:ADC should be
set as 1b'0.
The ADC clock is derived from the external 24MHz crystal source, with a frequency dividing factor that is configurable through the analog
register
SAR_ADC:CLKDIV:ADCDIV. The ADC clock frequency is F
ADC
= 24MHz / ( ADCDIV + 1 ).
14.1 ADC Control
14.1.1 ADC Channel Selection
The SAR ADC supports up to three channels including left channel, right channel and Misc channel, which are sampled sequentially. The
sampling sequence for each channel consists of a Set state and a Capture state. The bit of the analog register
SAR_ADC:CHEN:SCNT controls
the max state index. As shown in the figure below,
SCNT should be set to 6 to capture all three channels.
Figure 32. Conversion Sequence for all Channels
The left and Misc channel can be enabled independently through
SAR_ADC:CHEN:LEN and SAR_ADC:CHEN:MEN. When the left channel
is enabled, the right channel can be enabled through SAR_ADC:CHEN:REN. To sample mono audio signals, the left channel should be
enabled. To sample stereo audio signals, both the left channel and the right channel should be enabled.
14.1.2 ADC Set State
The length of Set state for left, right and Misc channel is configurable through the analog register
SAR_ADC:CAPCFG:ST. Set state duration
is defined as T
sd
= ST / 24MHz.
Each Set state serves to set ADC control signals for current channel through corresponding analog registers.
To select differential input mode
SAR_ADC:CHCFG:MODEL (left channel), SAR_ADC:CHCFG:MODER (right channel) or
SAR_ADC:CHCFG:MODEM (Misc channel) must be set as 1b'1.
The positive and negative inputs for left channel, right channel and Misc channel in differential mode are selected through the registers
SAR_ADC:CHL_INPUT, SAR_ADC:CHR_INPUT and SAR_ADC:CHM_INPUT. The positive input is selected through PCHSEL and the
negative input is selcted through
NCHSEL
Set reference voltage V
REF
with SAR_ADC:VREF_CTRL:VREFL (left channel), SAR_ADC:VREF_CTRL:VREFR (right channel) or
SAR_ADC:VREF_CTRL:VREFM (Misc channel). ADC maximum input range is the determined by the ADC reference voltage.
Set scaling factor for ADC analog input to 1 (default) or 1/8 SAR_ADC:APSC:VAL. By setting this scaling factor, ADC maximum input range
can be extended based on the V
REF
.
For example, suppose the V
REF
is set as 1.2V:
Since the scaling factor is 1 by default, the ADC maximum input range should be 0 to 1.2V (negative input is GND) and -1.2V to +1.2V (negative
input is ADC GPIO pin). If the scaling factor is set as 1/8, in theory ADC maximum input range should change to 0 to 9.6V (negative input is
GND) and -9.6V to +9.6V (negative input is ADC GPIO pin). But limited by input voltage of the chips PAD, the actual range is narrower. Set
resolution as 8/10/12/14 bits with
SAR_ADC:CHCFG:RESL (left channel), SAR_ADC:CHCFG:RESR or SAR_ADC:CHCFG:RESM (Misc
channel).