User's Manual

RYZ012 Multi-Standard Wireless Communication Module for Bluetooth 5 Low Energy and 802.15.4
R15UH0002EU0103 Rev.1.03 Page 28 of 206
Apr.21.21
3.4 Clock
The MCU of the RYZ012 provides low and high-speed clocks with versatile configuration options to optimize the power consumption and system
performance. The CPU clock and most of the peripheral clocks are derived from a 24 MHz high speed clock. The low speed clock is used to
drive the digital microphone peripheral and the low power timer (LP_TIMER), which can be kept running in suspend and deep sleep modes.
The MCU integrates RC oscillators for both of these clocks and provides the option to connect an external crystal oscillator for higher precision
clocks.
After power on the internal oscillators are selected as clock sources. The application firmware can change this to a suitable configuration. The
figure below gives an overview of the clock tree and shows the registers that are required to change the configuration of the clock tree.
Most peripheral clocks are gated through register
SCTL:PCEN by default. The application firmware must enable the clocks of the peripheral
units that are used by the application.
Figure 7. Clock Tree
3.4.1 System Clock
The system clock is selected from one of four possible sources. This can be either the 24 MHz RC clock, the internal clock HS1, HS1D that is
HS1 divided by
SCTL:HSC1:SCD or a fixed frequency 32 MHz clock derived from the high speed crystal oscillator. System clock selection is
done through
SCTL:HSC1:SCS.
Caution: For the HS1 clock divider, it must be ensured that SCTL:HSC1:SCD is never set to 0 or 1. The output frequency of the HS1 clock
divider clock is F
HS1D
=F
HS1
/SCTL:HSC1:SCD. The only way to select the maximum clock of 48 MHz is by setting both, SCTL:HSC1:HS0S
and
SCTL:HSC2:HS1S to 1b'0 and SCTL:HSC1:SCS to 2b'01.