User's Manual

R01UH0823EJ0110 Rev.1.10 Page 210 of 1852
Nov 30, 2020
RX23W Group 9. Clock Generation Circuit
9.7 PLL Circuit
The PLL circuit has a function to multiply the frequency from the oscillator.
9.8 Internal Clock
Clock sources of internal clock signals are the main clock, sub-clock, HOCO clock, LOCO clock, PLL clock,
USB-dedicated PLL clock, and dedicated low-speed clock for the IWDT. The internal clocks listed below are produced
from these sources.
(1) Operating clock of the CPU, DMAC, DTC, ROM, and RAM: System clock (ICLK)
(2) Operating clock of peripheral modules: Peripheral module clock (PCLKA, PCLKB, and PCLKD)
(3) Operating clock of the FlashIF: FlashIF clock (FCLK)
(4) Operating clock of USB modules: USB clock (UCLK)
(5) Operating clock of CAN modules: CAN clock (CANMCLK)
(6) Operating clock for the CAC: CAC clock (CACCLK)
(7) Operating clock for the RTC: RTC-dedicated sub-clock (RTCSCLK)
(8) Operating clock for the IWDT: IWDT-dedicated low-speed clock (IWDTCLK)
(9) Operating clock for the SSI: SSI clock (SSISCK)
(10) Operating clocks for BLE: The Bluetooth-dedicated clock (BLECLK), and the Bluetooth-dedicated low-speed
clock (BLELOCO)
(11) Operating clock for the low-power timer: LPT clock (LPTCLK)
Frequencies of the internal clocks are set by the combination of the divisors selected by the SCKCR.FCK[3:0], ICK[3:0],
PCKA[3:0], PCKB[3:0], and PCKD[3:0] bits, the clock source selected by the SCKCR3.CKSEL[2:0] bits, and the bits
that select the frequency of the PLL circuit (PLLCR.STC[5:0] and PLIDIV[1:0] bits, UPLLCR.UPLIDIV[1:0],
USTC[5:0] bits, and HOCOCR2.HCFRQ[1:0] bits). If the value of any of these bits is changed, subsequent operation
will be at the frequency determined by the new value.
9.8.1 System Clock
The system clock (ICLK) is used as the operating clock of the CPU, DMAC, DTC, ROM, and RAM.
The ICLK frequency is specified by the SCKCR.ICK[3:0] bits, and the SCKCR3.CKSEL[2:0] bits, and the
PLLCR.STC[5:0] and PLIDIV[1:0] bits.
9.8.2 Peripheral Module Clock
The peripheral module clocks (PCLKA, PCLKB, and PCLKD) are the operating clocks for use by peripheral modules.
The PCLKA, PCLKB, and PCLKD frequencies are specified by the SCKCR.PCKA[3:0], PCKB[3:0], and PCKD[3:0]
bits, the SCKCR3.CKSEL[2:0] bits, and the PLLCR.STC[5:0] and PLIDIV[1:0] bits.
The peripheral module clock used as the operating clock is PCLKD for S12AD, and PCLKA and PCLKB are for other
modules.
9.8.3 FlashIF Clock
The FlashIF clock (FCLK) is used as the operating clock of the FlashIF.
The FCLK frequency is specified by the SCKCR.FCK[3:0] bits, and the SCKCR3.CKSEL[2:0] bits, and the
PLLCR.STC[5:0] and PLIDIV[1:0] bits.