User's Manual
Table Of Contents
- Cover
- Notice
- General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products
- How to Use This Manual
- Contents
- Features
- 1. Overview
- 2. CPU
- 2.1 Features
- 2.2 Register Set of the CPU
- 2.2.1 General-Purpose Registers (R0 to R15)
- 2.2.2 Control Registers
- 2.2.2.1 Interrupt Stack Pointer (ISP)/User Stack Pointer (USP)
- 2.2.2.2 Exception Table Register (EXTB)
- 2.2.2.3 Interrupt Table Register (INTB)
- 2.2.2.4 Program Counter (PC)
- 2.2.2.5 Processor Status Word (PSW)
- 2.2.2.6 Backup PC (BPC)
- 2.2.2.7 Backup PSW (BPSW)
- 2.2.2.8 Fast Interrupt Vector Register (FINTV)
- 2.2.2.9 Floating-Point Status Word (FPSW)
- 2.2.3 Accumulator
- 2.3 Processor Mode
- 2.4 Data Types
- 2.5 Endian
- 2.6 Vector Table
- 2.7 Operation of Instructions
- 2.8 Number of Cycles
- 3. Operating Modes
- 4. Address Space
- 5. I/O Registers
- 6. Resets
- 7. Option-Setting Memory (OFSM)
- 8. Voltage Detection Circuit (LVDAb)
- 9. Clock Generation Circuit
- 9.1 Overview
- 9.2 Register Descriptions
- 9.2.1 System Clock Control Register (SCKCR)
- 9.2.2 System Clock Control Register 3 (SCKCR3)
- 9.2.3 PLL Control Register (PLLCR)
- 9.2.4 PLL Control Register 2 (PLLCR2)
- 9.2.5 USB-dedicated PLL Control Register (UPLLCR)
- 9.2.6 USB-dedicated PLL Control Register 2 (UPLLCR2)
- 9.2.7 Main Clock Oscillator Control Register (MOSCCR)
- 9.2.8 Sub-Clock Oscillator Control Register (SOSCCR)
- 9.2.9 Low-Speed On-Chip Oscillator Control Register (LOCOCR)
- 9.2.10 IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR)
- 9.2.11 High-Speed On-Chip Oscillator Control Register (HOCOCR)
- 9.2.12 High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2)
- 9.2.13 Oscillation Stabilization Flag Register (OSCOVFSR)
- 9.2.14 Oscillation Stop Detection Control Register (OSTDCR)
- 9.2.15 Oscillation Stop Detection Status Register (OSTDSR)
- 9.2.16 Main Clock Oscillator Wait Control Register (MOSCWTCR)
- 9.2.17 CLKOUT Output Control Register (CKOCR)
- 9.2.18 Main Clock Oscillator Forced Oscillation Control Register (MOFCR)
- 9.2.19 Memory Wait Cycle Setting Register (MEMWAIT)
- 9.2.20 Low-Speed On-Chip Oscillator Trimming Register (LOCOTRR)
- 9.2.21 IWDT-Dedicated On-Chip Oscillator Trimming Register (ILOCOTRR)
- 9.2.22 High-Speed On-Chip Oscillator Trimming Register n (HOCOTRRn) (n = 0, 3)
- 9.3 Main Clock Oscillator
- 9.4 Sub-Clock Oscillator
- 9.5 Dedicated Clock Oscillator for Bluetooth
- 9.6 Oscillation Stop Detection Function
- 9.7 PLL Circuit
- 9.8 Internal Clock
- 9.9 Usage Notes
- 10. Clock Frequency Accuracy Measurement Circuit (CAC)
- 10.1 Overview
- 10.2 Register Descriptions
- 10.2.1 CAC Control Register 0 (CACR0)
- 10.2.2 CAC Control Register 1 (CACR1)
- 10.2.3 CAC Control Register 2 (CACR2)
- 10.2.4 CAC Interrupt Request Enable Register (CAICR)
- 10.2.5 CAC Status Register (CASTR)
- 10.2.6 CAC Upper-Limit Value Setting Register (CAULVR)
- 10.2.7 CAC Lower-Limit Value Setting Register (CALLVR)
- 10.2.8 CAC Counter Buffer Register (CACNTBR)
- 10.3 Operation
- 10.4 Interrupt Requests
- 10.5 Usage Notes
- 11. Low Power Consumption
- 11.1 Overview
- 11.2 Register Descriptions
- 11.2.1 Standby Control Register (SBYCR)
- 11.2.2 Module Stop Control Register A (MSTPCRA)
- 11.2.3 Module Stop Control Register B (MSTPCRB)
- 11.2.4 Module Stop Control Register C (MSTPCRC)
- 11.2.5 Module Stop Control Register D (MSTPCRD)
- 11.2.6 Operating Power Control Register (OPCCR)
- 11.2.7 Sub Operating Power Control Register (SOPCCR)
- 11.2.8 Sleep Mode Return Clock Source Switching Register (RSTCKCR)
- 11.3 Reducing Power Consumption by Switching Clock Signals
- 11.4 Module Stop Function
- 11.5 Function for Lower Operating Power Consumption
- 11.6 Low Power Consumption Modes
- 11.7 Usage Notes
- 12. Battery Backup Function
- 13. Register Write Protection Function
- 14. Exception Handling
- 15. Interrupt Controller (ICUb)
- 15.1 Overview
- 15.2 Register Descriptions
- 15.2.1 Interrupt Request Register n (IRn) (n = interrupt vector number)
- 15.2.2 Interrupt Request Enable Register m (IERm) (m = 02h to 1Fh)
- 15.2.3 Interrupt Source Priority Register n (IPRn) (n = interrupt vector number)
- 15.2.4 Fast Interrupt Set Register (FIR)
- 15.2.5 Software Interrupt Generation Register (SWINTR)
- 15.2.6 DTC Transfer Request Enable Register n (DTCERn) (n = interrupt vector number)
- 15.2.7 DMAC Trigger Select Register m (DMRSRm) (m = DMAC channel number)
- 15.2.8 IRQ Control Register i (IRQCRi) (i = 0, 1, and 4 to 7)
- 15.2.9 IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0)
- 15.2.10 IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0)
- 15.2.11 Non-Maskable Interrupt Status Register (NMISR)
- 15.2.12 Non-Maskable Interrupt Enable Register (NMIER)
- 15.2.13 Non-Maskable Interrupt Status Clear Register (NMICLR)
- 15.2.14 NMI Pin Interrupt Control Register (NMICR)
- 15.2.15 NMI Pin Digital Filter Enable Register (NMIFLTE)
- 15.2.16 NMI Pin Digital Filter Setting Register (NMIFLTC)
- 15.3 Vector Table
- 15.4 Interrupt Operation
- 15.5 Non-maskable Interrupt Operation
- 15.6 Return from Power-Down States
- 15.7 Usage Note
- 16. Buses
- 17. Memory-Protection Unit (MPU)
- 17.1 Overview
- 17.2 Register Descriptions
- 17.2.1 Region-n Start Page Number Register (RSPAGEn) (n = 0 to 7)
- 17.2.2 Region-n End Page Number Register (REPAGEn) (n = 0 to 7)
- 17.2.3 Memory-Protection Enable Register (MPEN)
- 17.2.4 Background Access Control Register (MPBAC)
- 17.2.5 Memory-Protection Error Status-Clearing Register (MPECLR)
- 17.2.6 Memory-Protection Error Status Register (MPESTS)
- 17.2.7 Data Memory-Protection Error Address Register (MPDEA)
- 17.2.8 Region Search Address Register (MPSA)
- 17.2.9 Region Search Operation Register (MPOPS)
- 17.2.10 Region Invalidation Operation Register (MPOPI)
- 17.2.11 Instruction-Hit Region Register (MHITI)
- 17.2.12 Data-Hit Region Register (MHITD)
- 17.3 Functions
- 17.4 Procedures for Using Memory Protection
- 18. DMA Controller (DMACA)
- 18.1 Overview
- 18.2 Register Descriptions
- 18.2.1 DMA Source Address Register (DMSAR)
- 18.2.2 DMA Destination Address Register (DMDAR)
- 18.2.3 DMA Transfer Count Register (DMCRA)
- 18.2.4 DMA Block Transfer Count Register (DMCRB)
- 18.2.5 DMA Transfer Mode Register (DMTMD)
- 18.2.6 DMA Interrupt Setting Register (DMINT)
- 18.2.7 DMA Address Mode Register (DMAMD)
- 18.2.8 DMA Offset Register (DMOFR)
- 18.2.9 DMA Transfer Enable Register (DMCNT)
- 18.2.10 DMA Software Start Register (DMREQ)
- 18.2.11 DMA Status Register (DMSTS)
- 18.2.12 DMA Activation Source Flag Control Register (DMCSL)
- 18.2.13 DMA Module Activation Register (DMAST)
- 18.3 Operation
- 18.4 Ending DMA Transfer
- 18.5 Interrupts
- 18.6 Event Link Function
- 18.7 Low Power Consumption Function
- 18.8 Usage Notes
- 18.8.1 DMA Transfer to Peripheral Modules
- 18.8.2 Access to the Registers during DMA Transfer
- 18.8.3 DMA Transfer to Reserved Areas
- 18.8.4 Interrupt Request by the DMA Activation Source Flag Control Register (DMCSL) at the End of each Transfer
- 18.8.5 Setting of DMAC Activation Source Select Register of the Interrupt Controller (ICU.DMRSRm)
- 18.8.6 Suspending or Restarting DMA Activation
- 19. Data Transfer Controller (DTCa)
- 19.1 Overview
- 19.2 Register Descriptions
- 19.2.1 DTC Mode Register A (MRA)
- 19.2.2 DTC Mode Register B (MRB)
- 19.2.3 DTC Transfer Source Register (SAR)
- 19.2.4 DTC Transfer Destination Register (DAR)
- 19.2.5 DTC Transfer Count Register A (CRA)
- 19.2.6 DTC Transfer Count Register B (CRB)
- 19.2.7 DTC Control Register (DTCCR)
- 19.2.8 DTC Vector Base Register (DTCVBR)
- 19.2.9 DTC Address Mode Register (DTCADMOD)
- 19.2.10 DTC Module Start Register (DTCST)
- 19.2.11 DTC Status Register (DTCSTS)
- 19.3 Request Sources
- 19.4 Operation
R01UH0823EJ0110 Rev.1.10 Page 51 of 1852
Nov 30, 2020
RX23W Group
Renesas MCUs
Features
■ 32-bit RXv2 CPU core
• Max. operating frequency: 54 MHz
Capable of 88.56 DMIPS in operation at 54 MHz
• Enhanced DSP: 32-bit multiply-accumulate and 16-bit
multiply-subtract instructions supported
• Built-in FPU: 32-bit single-precision floating point (compliant to
IEEE754)
• Divider (fastest instruction execution takes two CPU clock cycles)
• Fast interrupt
• CISC Harvard architecture with 5-stage pipeline
• Variable-length instructions, ultra-compact code
• On-chip debugging circuit
• Memory protection unit (MPU) supported
■ Low power design and architecture
• Operation from a single 1.8-V to 3.6-V supply
• RTC capable of operating on the battery backup power supply
• Three low power consumption modes
• Low power timer (LPT) that operates during the software standby state
■ On-chip flash memory for code
• 384- to 512-Kbyte capacities
• On-board or off-board user programming
• Programmable at 1.8 V
• For instructions and operands
■ On-chip data flash memory
• 8 Kbytes (1,000,000 program/erase cycles (typ.))
• BGO (Background Operation)
■ On-chip SRAM, no wait states
• 64-Kbyte size capacities
■ Data transfer functions
• DMAC: Incorporates four channels
• DTC: Four transfer modes
■ ELC
• Module operation can be initiated by event signals without using
interrupts.
• Linked operation between modules is possible while the CPU is sleeping.
■ Reset and supply management
• Eight types of reset, including the power-on reset (POR)
• Low voltage detection (LVD) with voltage settings
■ Clock functions
• Main clock oscillator frequency: 1 to 20 MHz
• External clock input frequency: Up to 20 MHz
• Sub-clock oscillator frequency: 32.768 kHz
• Frequency of Bluetooth-dedicated clock oscillator: 32 MHz
• PLL circuit input: 4 MHz to 12.5 MHz
• On-chip low- and high-speed oscillators, dedicated on-chip low-speed
oscillator for the IWDT
• USB-dedicated PLL circuit: 4, 6, 8, or 12 MHz
54 MHz can be set for the system clock and 48 MHz for the USB clock
• Generation of a dedicated 32.768-kHz clock for the RTC
• Clock frequency accuracy measurement circuit (CAC)
■ Realtime clock
• Adjustment functions (30 seconds, leap year, and error)
• Calendar count mode or binary count mode selectable
• Time capture function
• Time capture on event-signal input through external pins
■ Independent watchdog timer
• 15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
■ Useful functions for IEC60730 compliance
• Self-diagnostic and disconnection-detection assistance functions for
the A/D converter, clock frequency accuracy measurement circuit,
independent watchdog timer, RAM test assistance functions using the
DOC, etc.
■ Capacitive touch sensing unit
• Self-capacitance method: A single pin configures a single key,
supporting up to 12 keys
• Mutual capacitance method: Matrix configuration with 12 pins, supporting
up to 36 keys
■ Up to 12 communication functions
• Bluetooth Low Energy (1 channel)
An RF transceiver and link layer compliant with the Bluetooth 5.0 Low
Energy specification
LE 1M PHY, LE 2M PHY, LE Coded PHY (125 kbps and 500 kbps),
and LE Advertising extension support
On-chip Bluetooth-dedicated AES-CCM (128-bit blocks) encryption
circuit
The 83-pin LGA product has been certified as compliant with radio-
related laws (in Japan, North America, and Europe).
The 83-pin LGA product includes a small PCB trace antenna.
• USB 2.0 host/function/On-The-Go (OTG) (one channel),
full-speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and
BC (Battery Charger) supported
• CAN (one channel) compliant to ISO11898-1:
Transfer at up to 1 Mbps
• SCI with many useful functions (up to 4 channels)
Asynchronous mode, clock synchronous mode, smart card interface
Reduction of errors in communications using the bit modulation
function
• IrDA interface (one channel, in cooperation with the SCI5)
• I
2
C bus interface: Transfer at up to 400 kbps, capable of SMBus
operation (one channel)
• RSPI (one channel): Transfer at up to 16 Mbps
• Serial sound interface (one channel)
• SD host interface (optional: one channel) SD memory/ SDIO 1-bit or
4-bit SD bus supported
■ Up to 19 extended-function timers
• 16-bit MTU: input capture, output compare, complementary PWM
output, phase counting mode (five channels)
• 16-bit TPU: input capture, output compare, phase counting mode (six
channels)
• 8-bit TMR (four channels)
• 16-bit compare-match timers (four channels)
■ 12-bit A/D converter
• Capable of conversion within 0.83 μs
• 14 channels
• Sampling time can be set for each channel
• Self-diagnostic function and analog input disconnection detection
assistance function
■ 12-bit D/A converter
• Two channels
■ Analog comparator
• Two channels × one unit
■ General I/O ports
• 5-V tolerant, open drain, input pull-up, switching of driving capacity
■ Encryption functions (TSIP-Lite)
• Unauthorized access to the encryption engine is disabled and
imposture and falsification of information are prevented
• Safe management of keys
• 128- or 256-bit key length of AES for ECB, CBC, GCM, others
• True random number generator
■ Temperature sensor
■ Operating temperature range
•−40 to +85°C
■ Applications
• 85-pin BGA, 56-pin QFN: General industrial and consumer equipment
• 83-pin LGA: Consumer equipment
PTLG0083KA-A 6.1 × 9.5 mm, 0.5 mm pitch
PTBG0085KB-A 5.5 × 5.5 mm, 0.5 mm pitch
PVQN0056LA-A 7 × 7 mm, 0.4 mm pitch
54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory,
Bluetooth
5.0, various communication functions including USB 2.0 full-speed host/function/OTG, CAN,
SD host interface, serial sound interface, capacitive touch sensing unit, 12-bit A/D converter,
12-bit D/A converter, RTC, Encryption functions
R01UH0823EJ0110
Rev.1.10
Nov 30, 2020