Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1099 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
(2) Break Field Low Width Determination Mode
This mode is for determining the Break Field low width in the input signal on the RXDX12 pin at the reception of a Start
Frame. Setting the TMR.TOMS[1:0] bits to 01b switches operation to Break Field low width determination mode. The
TMR.TCSS[2:0] bits select the clock source for the counter. When the TCR.TCST bit is set to 1, the interface enters the
Break Field low width determinable state. Determination starts when a low level is input from the RXDX12 pin. When a
high level is then input on the RXDX12 pin, registers TPRE and TCNT are reloaded and the interface enters the Break
Field low width determinable state. When the timer underflows during Break Field low width determination, the
STR.BFDF flag is set to 1. An SCIX0 interrupt is also generated if the value of the ICR.BFDIE bit is 1. If an underflow
of the timer during data transfer cause a problem in the form of interrupt generation, stop the timer after Break Field low
width determination.
Figure 33.74 shows an example of operations in Break Field low width output mode.
Figure 33.74 Example of Operations in Break Field Low Width Determination Mode
(3) Timer Mode
This mode is for counting cycles of the internal clock as the clock source. Setting the TMR.TOMS[1:0] bits to 00b
switches operation to timer mode. The TMR.TCSS[2:0] bits select the clock source for the counter. Counting starts when
1 is written to the TCR.TCST bit and stops when 0 is written to the TCST bit. Registers TPRE and TCNT both count
down. The TPRE register counts cycles of the clock source for counting, and underflows of the TPRE register provide
the clock source for counting by the TCNT register. When the timer underflows, the STR.BFDF flag is set to 1. An
SCIX0 interrupt is also generated if the value of the ICR.BFDIE bit is 1.
FFFFh
n
0000h
Determination
started
TCR.TCST
RXDX12 pin output
STR.BFDF
Determinable
state after
reloading
Underflow
Write 1 to
STCR.BFDCL
n = Contents of (upper) TCNT and (lower) TPRE
The above diagram assumes the following:
ESMER: ESME = 1
CR1: BFE = 0
PCR: RXDXPS = 0
ICR: BFDIE = 1
TMR: TOMS[1:0] = 01b
Contents of the counter (hex.)
Determination
started
Determinable
state after
reloading
Set to 1 by a program