Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1102 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.12.3 Interrupts in Smart Card Interface Mode
Table 33.32 lists interrupt sources in smart card interface mode. A transmit end interrupt (TEI) request cannot be used in
this mode.
Table 33.32 SCI Interrupt Sources
Data transmission/reception using the DTC or DMAC is also possible in smart card interface mode, similar to in the
normal SCI mode. In transmission, when the SSR.TEND flag is set to 1, a TXI interrupt request is generated. This TXI
interrupt request activates the DTC or DMAC allowing transfer of transmit data if the TXI request is specified
beforehand as a source of DTC or DMAC activation. The TEND flag is automatically set to 0 when the DTC or DMAC
transfers the data.
If an error occurs, the SCI automatically retransmits the same data. During the retransmission, the TEND flag is kept to 0
and the DTC or DMAC is not activated. Therefore, the SCI and DTC or DMAC automatically transmit the specified
number of bytes, including retransmission in the case of error occurrence. However, the SSR.ERS flag is not
automatically cleared to 0 at error occurrence. Therefore, the ERS flag must be cleared by previously setting the
SCR.RIE bit to 1 to enable an ERI interrupt request to be generated at error occurrence.
When transmitting/receiving data using the DTC or DMAC, be sure to make settings to enable the DTC or DMAC
before making SCI settings. For DTC or DMAC settings, refer to
section 19, Data Transfer Controller (DTCa) and
section 18, DMA Controller (DMACA).
In reception, an RXI interrupt request is generated when receive data is set to the RDR register. This RXI interrupt
request activates the DTC or DMAC allowing transfer of receive data if the RXI request is specified beforehand as a
source of DTC or DMAC activation. If an error occurs, the error flag is set. Therefore, the DTC or DMAC is not
activated and an ERI interrupt request is issued to the CPU instead; the error flag must be cleared.
Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation
ERI Receive error or error signal detection ORER, PER, or ERS Not possible Not possible
RXI Receive data full — Possible Possible
TXI Transmit data empty TEND Possible Possible