Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1103 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.12.4 Interrupts in Simple I
2
C Mode
The interrupt sources in simple I
2
C mode are listed in Table 33.33. The STI interrupt is allocated to the transmit end
interrupt (TEI) request. The receive error interrupt (ERI) request cannot be used.
The DTC or DMAC can also be used to handle transfer in simple I
2
C mode.
When the value of the SIMR2.IICINTM bit is 1, an RXI request will be generated on the falling edge of the SSCLn
signal for the eighth bit. If the RXI has been set up as an activating request for the DTC or DMAC beforehand, the RXI
request will activate the DTC or DMAC to handle transfer of the received data. Furthermore, a TXI request is generated
on the falling edge of the SSCLn signal for the ninth bit (acknowledge bit). If the TXI has been set up as an activating
request for the DTC or DMAC beforehand, the TXI request will activate the DTC or DMAC to handle transfer of the
transmit data.
When the value of the SIMR2.IICINTM bit is 0, an RXI request (ACK detection) if the input on the SSDAn pin is at the
low level or a TXI request (NACK detection) if the input on the SSDAn pin is at the high level will be generated on the
rising edge of the SSCLn signal for the ninth bit (acknowledge bit). If the RXI has been set up as an activating request for
the DTC or DMAC beforehand, the RXI request will activate the DTC or DMAC to handle transfer of the received data.
Also, if the DTC or DMAC is used for data transfer in reception or transmission, be sure to set up and enable the DTC or
DMAC before setting up the SCI.
When the IICSTAREQ, IICRSTAREQ, and IICSTPREQ bits in the SIMR3 register are used to generate a start condition,
restart condition, or stop condition, the STI request is issued when generation is complete.
Table 33.33 SCI Interrupt Sources
Note 1. Activation of the DTC or DMAC is only possible when the SIMR2.IICINTM bit is 1 (use reception and transmission interrupts).
Name
Interrupt Source
Interrupt Flag DTC Activation DMAC ActivationIICINTM bit = 0 IICINTM bit = 1
RXI ACK detection Reception — Possible Possible
TXI NACK detection Transmission — Possible*
1
Possible*
1
STI Completion of generation of a start,
restart, or stop condition
IICSTIF Not possible Not possible