Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1104 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.12.5 Interrupt Requests from the Extended Serial Mode Control Section
The extended serial mode control section has a total of six types of interrupt request for generating the SCIX0 interrupt
(Break Field low width detected), SCIX1 interrupt (Control Field 0 match, Control Field 1 match, priority interrupt bit
detected), SCIX2 interrupt (bus collision detected), and SCIX3 interrupt (valid edge detected). When any of the interrupt
factors is generated, the corresponding status flag is set to 1. Details of all of the interrupt requests are listed in
Table
33.34
.
Table 33.34 Interrupt Sources of the Extended Serial Mode Control Section
Interrupt Request Status Flag Interrupt Factors
SCIX0 interrupt (Break Field low width
detected)
BFDF • Detection of a Break Field low width longer than the interval corresponding
to the timer setting
• Completion of the output of a Break Field low width over the interval
corresponding to the timer setting
• Underflow of the timer
SCIX1 interrupt (Control Field 0 match) CF0MF The data received in Control Field 0 matching the value set in the CF0DR
register
SCIX1 interrupt (Control Field 1 match) CF1MF The data received in Control Field 1 matching the value set in the PCF1DR or
SCF1DR register
SCIX1 interrupt (priority interrupt bit
detected)
PIBDF The value of the bit specified as the priority interrupt bit matching the value set
in the PCF1DR register
SCIX2 interrupt (bus collision detected) BCDF The output level on the TXDX12 pin and the input level on the RXDX12 pin not
matching on three consecutive cycles of the bus collision detection clock
SCIX3 interrupt (valid edge detected) AEDF Detection of a valid edge during bit rate measurement