Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1107 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.14.6 Restrictions on Clock Synchronous Transmission (Clock Synchronous Mode
and Simple SPI Mode)
When the external clock source is used as a synchronization clock, the following restrictions apply.
(1) Start of transmission
Update the TDR register by the CPU, DMAC, or DTC and wait for at least five PCLK cycles before allowing the
transmit clock to be input (refer to
Figure 33.76).
(2) Continuous transmission
(a) Write the next transmit data to the TDR or TDRL register before the falling edge of the transmit clock (bit 7)
(refer to
Figure 33.76).
(b) When updating the TDR register after bit 7 has started to transmit, update the TDR register while the
synchronization clock is in the low-level period, and set the high-level width of the transmit clock (bit 7) to four
PCLK cycles or longer (refer to
Figure 33.76).
Figure 33.76 Restrictions on Use of External Clock in Clock Synchronous Transmission
D0 D1 D3 D4 D5 D7 D0
D2
D6
Synchronous clock
(external clock)
Serial transmit data
TXI interrupt flag
(ICU.IRn
*1
)
(1) Start of transmission and (2) Continuous transmission (a)
D0 D1 D3 D4 D5 D7 D0
D2
D6
Update TDR before bit 7 is started to transmit when
continuous transmission is performed on the external clock.
TDR
t
First frame of data
Next frame of data
Synchronous clock
(external clock)
Serial transmit data
TXI interrupt flag
(ICU.IRn
*1
)
(2) Continuous transmission (b)
TDR
Previous frame of data
Next frame of data
D1 D2
t
D1
D3
Set t ≥ 5 cycles of the PCLK before transmission is started when the external clock is used.
Set t
≥ 4 cycles of the PCLK if TDR is updated after bit 7 is started to transmit when continuous
transmission is performed on the external clock.
Note 1. Refer to section 15, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.