Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1112 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.14.11 Limitations on Simple SPI Mode
(1) Master Mode
• Use a resistor to pull up or pull down the clock line matching the initial settings for the transfer clock set by the
SPMR.CKPH and CKPOL bits when the SPMR.SSE bit is 1.
This prevents the clock line from being placed in the high-impedance state when the SCR.TE bit is set to 0 or
unexpected edges from being generated on the clock line when the SCR.TE bit is changed from 0 to 1. When the
SPMR.SSE bit is 0 in single master mode, pulling up or pulling down the clock line is not necessary because the
clock line is not placed in the high-impedance state even when the SCR.TE bit is set to 0.
• In the case of the setting for clock delay (SPMR.CKPH bit is 1), the receive data full interrupt (RXI) is generated
before the final clock edge on the SCKn pin as indicated in
Figure 33.81. If the TE and RE bits in the SCR register
become 0 at this time before the final edge of the clock signal on the SCKn pin, the SCKn pin is placed in the
high-impedance state, so the width of the last clock pulse of the transfer clock is shortened. Furthermore, an RXI
interrupt may lead to the input signal on the SSn# pin of a connected slave going to the high level before the final
edge of the clock signal on the SCKn pin, leading to incorrect operation of the slave.
• In a multi-master configuration, take care because the SCKn pin output becomes high-impedance while the input on
the SSn# pin is at the low level if a mode fault error occurs as the current character is being transferred, stopping
supply of the clock signal to the connected slave. Remake the settings for the connected slave to avoid misaligned
bits when transfer is restarted.
Figure 33.81 Timing of the RXI Interrupt in Simple SPI Mode (with Clock Delay)
(2) Slave Mode
• Secure at least five cycles of the PCLK from writing transmit data in the TDR register to start of the external clock
input. Also secure at least five cycles of the PCLK from input of low level on the SSn# pin to start of the external
clock input.
• Provide an external clock signal from the master the same as the transmit/receive data length.
• Control the input on the SSn# pin before the start and after the end of data transfer.
• When the level being input on the SSn# pin is to be changed from low to high while the current character is being
transferred, set the TE and RE bits in the SCR register to 0 and, after remaking the settings, restart transfer of the
first byte.
SCKn pin
(SPMR.CKPOL = 1)
SCKn pin
(SPMR.CKPOL = 0)
RXDn pin
Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 0
RXI source
Bit 7