Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1010 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.2.16 I
2
C Mode Register 2 (SIMR2)
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR register are 0 (serial reception and transmission
disabled).
SIMR2 is used to select how reception and transmission are controlled in simple I
2
C mode.
IICINTM Bit (I
2
C Interrupt Mode Select)
This bit selects the sources of interrupt requests in simple I
2
C mode.
IICCSC Bit (Clock Synchronization)
Set the IICCSC bit to 1 if the internally generated SSCLn clock signal is to be synchronized when the SSCLn pin has
been placed at the low level in the case of a wait inserted by the other device, etc.
The SSCLn clock signal is not synchronized if the IICCSC bit is 0. The SSCLn clock signal is generated in accord with
the rate selected in the BRR regardless of the level being input on the SSCLn pin.
Set the IICCSC bit to 1 except during debugging.
IICACKT Bit (ACK Transmission Data)
Transmitted data contains ACK bits. Set this bit to 1 when ACK and NACK bits are received.
Address(es): SCI1.SIMR2 0008 A02Ah, SCI5.SIMR2 0008 A0AAh, SCI8.SIMR2 0008 A10Ah, SCI12.SIMR2 0008 B30Ah
b7 b6 b5 b4 b3 b2 b1 b0
——
IICACK
T
———IICCSC
IICINT
M
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 IICINTM I
2
C Interrupt Mode Select 0: Use ACK/NACK interrupts.
1: Use reception and transmission interrupts.
R/W*
1
b1 IICCSC Clock Synchronization 0: No synchronization with the clock signal
1: Synchronization with the clock signal
R/W*
1
b4 to b2 — Reserved These bits are read as 0. The write value should be 0. R/W
b5 IICACKT ACK Transmission Data 0: ACK transmission
1: NACK transmission and reception of ACK/NACK
R/W
b7, b6 — Reserved These bits are read as 0. The write value should be 0. R/W