Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1118 of 1852
Nov 30, 2020
RX23W Group 34. IrDA Interface
34.3 Operation
34.3.1 Transmission
In transmission, the signals output from the SCI5 (UART frames) are converted to the IR frame data through the IrDA
interface (see
Figure 34.2). When the IRCR.IRTXINV bit is 0 and data is 0, high-level pulses with 3/16 of the bit period
are output (initial setting). The high-level pulse width can be changed by setting the IRCR.IRCKS[2:0] bits. The standard
prescribes that the minimum high-level pulse width should be 1.41 μs and the maximum high-level pulse width should
be the bit period × (3/16 + 2.5%) or (the bit period × 3/16) + 1.08 μs. When the peripheral module clock PCLK is 20
MHz, the minimum high-level pulse width can be set to 1.6 μs (101b: PCLK/32) as shown in
Table 34.2. When data is
1, no pulses are output.
Figure 34.2 IrDA Transmission/Reception
UART frame
Data
0101001101
Start bit Stop bit
11 1110000 0
IR frame
Data
Start bit Stop bit
Bit period
The pulse width is 1.4 µs to
the bit period x (3/16 + 2.5%)
or (the bit period × 3/16) + 1.08 µs
Transmission Reception