Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1120 of 1852
Nov 30, 2020
RX23W Group 34. IrDA Interface
34.4 Usage Notes
34.4.1 Module Stop Function Setting
The IrDA can be enabled and disabled using module stop control register C (MSTPCRC). The IrDA is stopped after a
reset. Registers can be accessed by releasing the module stop state. For details, refer to
section 11, Low Power
Consumption
.
34.4.2 SCI5 Setting
When using the IrDA, set the SCI5.SEMR.ABCS bit to 0 and SMR.STOP bit to 1 (2 stop bits).
34.4.3 Minimum Pulse-Width during Reception
For the input signals (IRRXD5) of this IrDA, input waveforms compliant to IrDA standard 1.0 (minimum pulse width:
1.4 us).
34.4.4 Notes on IrDA Initial Setting/Resetting
To change the value of the SCI5.SCR.TE or RE bit, set the IRCR.IRE bit to 1 (IrDA operates) and the IRCR.IRCKS[2:0]
bits to 000b and then use the following procedure.
(1) Enabling transmission
• After the SCI.SCR.TE bit is set to 1 (transmission is enabled), wait for a duration of 18/(16 × SCI5 bit rate) and then
switch the I/O port function to the IRTXD5 pin.
(2) Enabling reception
• After the I/O port function is switched to the IRTXD5 pin, wait for a duration of 18/(16 × SCI5 bit rate) and then set
the SCI.SCR.TE bit to 1 (transmission is enabled).
When performing transmission and reception, a duration of 18/(16 × SCI5 bit rate) can be waited at the same time.