Users Manual

R01UH0823EJ0110 Rev.1.10 Page 1121 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35. I
2
C-bus Interface (RIICa)
This MCU has a single-channel I
2
C-bus interface (RIIC).
The RIIC module conforms with the NXP I
2
C-bus (Inter-IC bus) interface and provides a subset of its functions.
In this section, “PCLK” is used to refer to PCLKB.
35.1 Overview
Table 35.1 lists the specifications of the RIIC, Figure 35.1 shows a block diagram of the RIIC, and Figure 35.2 shows
an example of I/O pin connections to external circuits (I
2
C-bus configuration example). Table 35.2 lists the I/O pins of
the RIIC.
Table 35.1 RIIC Specifications (1/2)
Item Description
Communications format • I
2
C-bus format or SMBus format
• Master mode or slave mode selectable
• Automatic securing of the various setup times, hold times, and bus-free times for the transfer rate
Transfer rate Fast-mode is supported (up to 400 kbps)
Serial clock (SCL) For master operation, the duty cycle of the SCL is selectable in the range from 4 to 96%.
Generating and
detecting conditions
Start, restart, and stop conditions are automatically generated. Start conditions (including restart conditions)
and stop conditions are detectable.
Slave address
• Up to three different slave addresses can be set.
• 7-bit and 10-bit address formats are supported (along with the use of both at once).
• General call addresses, device ID addresses, and SMBus host addresses are detectable.
Acknowledgment
• For transmission, the acknowledgment bit is automatically loaded.
Transfer of the next data for transmission can be automatically suspended on detection of a
not-acknowledge signal.
• For reception, the acknowledgment bit is automatically transmitted.
If a wait between the eighth and ninth clock pulses has been selected, software control of the
acknowledgment in response to the received data is possible.
Wait function
• During reception, cycles of waiting by holding the SCL line low can be inserted at the following two types
of timing:
Waiting between the eighth and ninth clock pulses
Waiting between the ninth clock pulse and the first clock pulse of the next byte
SDA output delay
function
Changes in the timing of the output of data bits for transmission, and of the acknowledgment bit, can be
delayed relative to the falling edge of SCL.
Arbitration
• For multi-master operation
Clock synchronization for the SCL line in cases of conflict with the SCL signal from another master is
possible.
When generating the start condition would create conflict on the bus, loss in arbitration is detected by
testing for non-matching between the internal data level and the actual level on the SDA line.
During master operation, loss in arbitration is detected by testing for non-matching between the actual
level on the SDA line and the internal data level.
• Loss in arbitration due to detection of the start condition while the bus is busy is detectable (to prevent the
generating of double start conditions).
• Loss in arbitration in transfer of a not-acknowledge signal due to the internal signal (NACK) and the actual
level on the SDA line not matching is detectable.
• Loss in arbitration due to non-matching of internal data level and the actual level on the SDA line is
detectable in slave transmission.
Timeout function The internal timeout function is capable of detecting long-interval stop of the SCL.
Noise cancellation The interface incorporates digital noise filters for both the SCL and SDA signals, and the width for noise
cancellation by the filters is adjustable by software.
Interrupt sources Four sources:
• Error in transfer or occurrence of events
Detection of arbitration-lost, NACK, timeout, a start condition including a restart condition, or a stop
condition
• Receive data full (including matching with a slave address)
• Transmit data empty (including matching with a slave address)
• Transmit end