Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1124 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.2 Register Descriptions
35.2.1 I
2
C-bus Control Register 1 (ICCR1)
SDAO Bit (SDA Output Control/Monitor) and SCLO Bit (SCL Output Control/Monitor)
These bits are used to directly control the SDA0 and SCL0 signals output from the RIIC.
When writing to these bits, also write 0 to the SOWP bit.
The result of setting these bits is input to the RIIC via the input buffer. When slave mode is selected, a start condition
may be detected and the bus may be released depending on the bit settings.
Do not rewrite these bits during a start condition, stop condition, restart condition, or during transmission or reception.
Operation after rewriting under the above conditions is not guaranteed.
When reading these bits, the state of signals output from the RIIC can be read.
Address(es): RIIC0.ICCR1 0008 8300h
b7 b6 b5 b4 b3 b2 b1 b0
ICE IICRST CLO SOWP SCLO SDAO SCLI SDAI
Value after reset:
00011111
Bit Symbol Bit Name Description
R/W
b0
SDAI SDA Line Monitor 0: SDA0 line is low.
1: SDA0 line is high.
R
b1
SCLI SCL Line Monitor 0: SCL0 line is low.
1: SCL0 line is high.
R
b2
SDAO SDA Output Control/Monitor
• Read:
0: The RIIC has driven the SDA0 pin low.
1: The RIIC has released the SDA0 pin.
• Write:
0: The RIIC drives the SDA0 pin low.
1: The RIIC releases the SDA0 pin.
(High level output is achieved through an external pull-up
resistor.)
R/W
b3
SCLO SCL Output Control/Monitor
• Read:
0: The RIIC has driven the SCL0 pin low.
1: The RIIC has released the SCL0 pin.
• Write:
0: The RIIC drives the SCL0 pin low.
1: The RIIC releases the SCL0 pin.
(High level output is achieved through an external pull-up
resistor.)
R/W
b4
SOWP SCLO/SDAO Write Protect 0: SCLO and SDAO bits can be written.
1: SCLO and SDAO bits are protected.
(This bit is read as 1.)
R/W
b5
CLO Additional SCL Output 0: Does not output an additional SCL (default).
1: Outputs an additional SCL.
(The CLO bit is cleared automatically after one clock pulse is
output.)
R/W
b6
IICRST I
2
C-bus Interface Internal
Reset
0: Releases the RIIC reset or internal reset.
1: Initiates the RIIC reset or internal reset.
(Clears the bit counter and the SCL0/SDA0 output latch)
R/W
b7
ICE I
2
C-bus Interface Enable 0: Disable (SCL0 and SDA0 pins in inactive state)
1: Enable (SCL0 and SDA0 pins in active state)
(Combined with the IICRST bit to select either RIIC or internal
reset.)
R/W