Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1126 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.2.2 I
2
C-bus Control Register 2 (ICCR2)
Note 1. When the ICMR1.MTWP bit is set to 1, bits MST and TRS can be written to.
ST Bit (Start Condition Generation Request)
This bit is used to request transition to master mode and generation of a start condition.
When this bit is set to 1 to request to generate a start condition, a start condition is generated when the BBSY flag is set
to 0 (bus free state).
For details on the start condition generation, refer to
section 35.10, Start Condition/Restart Condition/Stop
Condition Generating Function
.
[Setting condition]
• When 1 is written to the ST bit
[Clearing conditions]
• When 0 is written to the ST bit
• When a start condition has been generated (a start condition is detected)
• When the ICSR2.AL (arbitration-lost) flag is set to 1
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
Note: Set the ST bit to 1 (requests to generate a start condition) when the BBSY flag is set to 0 (bus free state).
Note that arbitration may be lost due to a start condition generation error if the ST bit is set to 1 (requests to
generate a start condition) when the BBSY flag is set to 1 (bus busy state).
Address(es): RIIC0.ICCR2 0008 8301h
b7 b6 b5 b4 b3 b2 b1 b0
BBSY MST TRS — SP RS ST —
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 — Reserved This bit is read as 0. The write value should be 0. R/W
b1 ST Start Condition Generation
Request
0: Does not request to generate a start condition.
1: Requests to generate a start condition.
R/W
b2 RS Restart Condition
Generation Request
0: Does not request to generate a restart condition.
1: Requests to generate a restart condition.
R/W
b3 SP Stop Condition Generation
Request
0: Does not request to generate a stop condition.
1: Requests to generate a stop condition.
R/W
b4 — Reserved This bit is read as 0. The write value should be 0. R/W
b5 TRS Transmit/Receive Mode 0: Receive mode
1: Transmit mode
R/W*
1
b6 MST Master/Slave Mode 0: Slave mode
1: Master mode
R/W*
1
b7 BBSY Bus Busy Detection Flag 0: The I
2
C-bus is released (bus free state).
1: The I
2
C-bus is occupied (bus busy state).
R