Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1127 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
RS Bit (Restart Condition Generation Request)
This bit is used to request that a restart condition be generated in master mode.
When this bit is set to 1 to request to generate a restart condition, a restart condition is generated when the BBSY flag is
set to 1 (bus busy state) and the MST bit is set to 1 (master mode).
For details on the restart condition generation, refer to
section 35.10, Start Condition/Restart Condition/Stop
Condition Generating Function
.
[Setting condition]
• When 1 is written to the RS bit with the ICCR2.BBSY flag set to 1
[Clearing conditions]
• When 0 is written to the RS bit
• When a restart condition has been generated (a start condition is detected)
• When the ICSR2.AL (arbitration-lost) flag is set to 1
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
Note: Do not set the RS bit to 1 while generating a stop condition.
Note: If 1 (requests to generate a restart condition) is written to the RS bit in slave mode, the restart condition is not
generated but the RS bit remains set to 1. If the operating mode changes to master mode with the bit not being
cleared, note that the restart condition may be generated.
SP Bit (Stop Condition Generation Request)
This bit is used to request that a stop condition be generated in master mode.
When this bit is set to 1 to request to generate a stop condition, a stop condition is generated when the BBSY flag is set to
1 (bus busy state) and the MST bit is set to 1 (master mode).
For details on the stop condition generation, refer to
section 35.10, Start Condition/Restart Condition/Stop
Condition Generating Function
.
[Setting condition]
• When 1 is written to the SP bit with both the BBSY flag and the ICCR2.MST bit set to 1
[Clearing conditions]
• When 0 is written to the SP bit
• When a stop condition has been generated (a stop condition is detected)
• When the ICSR2.AL (arbitration-lost) flag is set to 1
• When a start condition and a restart condition are detected
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
Note: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).
Note: Do not set the SP bit to 1 while a restart condition is being generated.