Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1011 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.2.17 I
2
C Mode Register 3 (SIMR3)
Note 1. Generate a start condition only when the SSCLn and SSDAn pins are both high (the corresponding bits in the corresponding
PIDR registers are 1).
Note 2. Generate a restart or stop condition only when the SSCLn pin is low (the corresponding bit in the PIDR register is 0).
Note 3. Do not set more than one from among the IICSTAREQ, IICRSTAREQ, and IICSTPREQ bits to 1 at a given time.
Note 4. Execute the generation of a condition after the value of the IICSTIF flag is 0.
Note 5. Do not write 0 to this bit while it is 1. Generation of a condition is suspended by writing 0 to this bit while it is 1.
SIMR3 is used to control the simple I
2
C mode start and stop conditions, and to hold the SSDAn and SSCLn pins at fixed
levels.
IICSTAREQ Bit (Start Condition Generation)
When a start condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b as well as setting the
IICSTAREQ bit to 1.
[Setting condition]
• Writing 1 to the bit
[Clearing condition]
• Completion of generation of the start condition
Address(es): SCI1.SIMR3 0008 A02Bh, SCI5.SIMR3 0008 A0ABh, SCI8.SIMR3 0008 A10Bh, SCI12.SIMR3 0008 B30Bh
b7 b6 b5 b4 b3 b2 b1 b0
IICSCLS[1:0] IICSDAS[1:0] IICSTIF
IICSTP
REQ
IICRST
AREQ
IICSTA
REQ
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 IICSTAREQ Start Condition Generation 0: A start condition is not generated.
1: A start condition is generated.*
1,
*
3,
*
4,
*
5
R/W
b1 IICRSTAREQ Restart Condition Generation 0: A restart condition is not generated.
1: A restart condition is generated.*
2,
*
3,
*
4,
*
5
R/W
b2 IICSTPREQ Stop Condition Generation 0: A stop condition is not generated.
1: A stop condition is generated.*
2,
*
3,
*
4,
*
5
R/W
b3 IICSTIF Issuing of Start, Restart, or Stop
Condition Completed Flag
0: There are no requests for generating conditions or a
condition is being generated.
1: A start, restart, or stop condition is completely generated.
R/W
b5, b4 IICSDAS[1:0] SSDA Output Select
b5 b4
0 0: Serial data output
0 1: Generate a start, restart, or stop condition.
1 0: Output the low level on the SSDAn pin.
1 1: Place the SSDAn pin in the high-impedance state.
R/W
b7, b6 IICSCLS[1:0] SSCL Output Select
b7 b6
0 0: Serial clock output
0 1: Generate a start, restart, or stop condition.
1 0: Output the low level on the SSCLn pin.
1 1: Place the SSCLn pin in the high-impedance state.
R/W