Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1128 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
TRS Bit (Transmit/Receive Mode)
This bit indicates transmit or receive mode.
The RIIC is in receive mode when the TRS bit is set to 0 and is in transmit mode when the bit is set to 1. Combination of
this bit and the MST bit indicates the operating mode of the RIIC.
The value of the TRS bit is automatically changed to 1 for transmission or 0 for reception in response to the generation or
detection of a start condition and setting of the R/W# bit. Although writing to the TRS bit is possible when the
ICMR1.MTWP bit is set to 1, writing to this bit is not necessary during normal usage.
[Setting conditions]
• When a start condition is generated normally according to the start condition generation request (when a start
condition is detected with the ST bit set to 1)
• When a restart condition is generated normally according to the restart condition generation request (when a restart
condition is detected with the RS bit set to 1)
• When the R/W# bit added to the slave address is set to 0 in master mode
• When the address received in slave mode matches the address enabled in the ICSER register, with the R/W# bit set
to 1
• When 1 is written to the TRS bit with the ICMR1.MTWP bit set to 1
[Clearing conditions]
• When a stop condition is detected
• The ICSR2.AL (arbitration-lost) flag being set to 1
• In master mode, reception of a slave address to which an R/W# bit with the value 1 is appended
• In slave mode, a match between the received address and the address enabled in the ICSER register when the value
of the received R/W# bit is 0 (including cases where the received address is the general call address)
• In slave mode, a restart condition is detected (that is, a start condition is detected while the ICCR2.BBSY flag is 1
and the ICCR2.MST bit is 0)
• When 0 is written to the TRS bit with the ICMR1.MTWP bit set to 1
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
MST Bit (Master/Slave Mode)
This bit indicates master or slave mode.
The RIIC is in slave mode when the MST bit is set to 0 and is in master mode when the bit is set to 1. Combination of this
bit and the TRS bit indicates the operating mode of the RIIC.
The value of the MST bit is automatically changed to 1 for master mode or 0 for slave mode by generating of a start
condition and generating or detection of a stop condition, etc. Although writing to the MST bit is possible when the
ICMR1.MTWP bit is set to 1, writing to this bit is not necessary during normal usage.
[Setting conditions]
• When a start condition is generated normally according to the start condition generation request (when a start
condition is detected with the ST bit set to 1)
• When 1 is written to the MST bit with the ICMR1.MTWP bit set to 1
[Clearing conditions]
• When a stop condition is detected
• When the ICSR2.AL (arbitration-lost) flag is set to 1
• When 0 is written to the MST bit with the ICMR1.MTWP bit set to 1
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset