Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1132 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
TMOL Bit (Timeout L Count Control)
This bit is used to enable or disable the internal counter of the timeout function to count up while the SCL0 line is held
low when the timeout function is enabled (ICFER.TMOE bit is 1).
TMOH Bit (Timeout H Count Control)
This bit is used to enable or disable the internal counter of the timeout function to count up while the SCL0 line is held
high when the timeout function is enabled (ICFER.TMOE bit is 1).
SDDL[2:0] Bits (SDA Output Delay Counter)
The SDA output can be delayed by the SDDL[2:0] setting. This counter works with the clock source selected by the
DLCS bit. The setting of this function can be used for all types of SDA output, including the transmission of the
acknowledgment bit.
Set the SDA output delay time to meet the I
2
C-bus specification (within the data valid time/data valid acknowledge
time
*
1
) or the SMBus specification (more than the data hold time (300 ns) and less than “clock low period – data setup
time (250 ns)”). Note that, if a value outside the specification is set, communication with communication devices may
malfunction or it may seemingly become a start condition or stop condition depending on the bus state.
For details on this function, refer to
section 35.5, SDA Output Delay Function.
Note 1. Data valid time/data valid acknowledge time
3,450 ns (up to 100 kbps: Standard-mode (Sm))
900 ns (up to 400 kbps: Fast-mode (Fm))