Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1134 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
ACKBR Bit (Received Acknowledge)
This bit is used to store the value of the acknowledgment bit received from the receiver in transmit mode.
[Setting condition]
• When 1 is received as the acknowledgment bit with the ICCR2.TRS bit set to 1
[Clearing conditions]
• When 0 is received as the acknowledgment bit with the ICCR2.TRS bit set to 1
• When 1 is written to the ICCR1.IICRST bit while the ICCR1.ICE bit is 0 (RIIC reset)
ACKBT Bit (Transmit Acknowledge)
This bit is used to set the bit to be sent at the acknowledgment timing in receive mode.
[Setting condition]
• When 1 is written to this bit with the ACKWP bit set to 1
[Clearing conditions]
• When 0 is written to this bit with the ACKWP bit set to 1
• When stop condition generation is detected (when a stop condition is detected with the ICCR2.SP bit set to 1)
• When 1 is written to the ICCR1.IICRST bit while the ICCR1.ICE bit is 0 (RIIC reset)
ACKWP Bit (ACKBT Write Protect)
This bit is used to control the modification of the ACKBT bit.
RDRFS Bit (RDRF Flag Set Timing Select)
This bit is used to select the RDRF flag set timing in receive mode and also to select whether to hold the SCL0 line low
at the falling edge of the eighth SCL.
When the RDRFS bit is 0, the SCL0 line is not held low at the falling edge of the eighth SCL, and the RDRF flag is set to
1 at the rising edge of the ninth SCL.
When the RDRFS bit is 1, the RDRF flag is set to 1 at the rising edge of the eighth SCL and the SCL0 line is held low at
the falling edge of the eighth SCL. The low-hold of the SCL0 line is released by writing a value to the ACKBT bit.
After data is received with this setting, the SCL0 line is automatically held low before the acknowledgment bit is sent.
This enables processing to send ACK (ACKBT bit is 0) or NACK (ACKBT bit is 1) according to receive data.
WAIT Bit (WAIT)
This bit is used to control whether to hold the period between the ninth SCL and the first SCL low until the I
2
C-bus
receive data register (ICDRR) is completely read each time single-byte data is received in receive mode.
When the WAIT bit is 0, the receive operation is continued without holding the period between the ninth and the first
SCL low. When both the RDRFS and WAIT bits are 0, continuous receive operation is enabled with the double buffer.
When the WAIT bit is 1, the SCL0 line is held low from the falling edge of the ninth SCL until the ICDRR register value
is read each time single-byte data is received. This enables receive operation in byte units.
Note: When the value of the WAIT bit is to be read, be sure to read the ICDRR register beforehand.
SMBS Bit (SMBus/I
2
C-bus Select)
Setting this bit to 1 selects the SMBus and enables the ICSER.HOAE bit.