Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1146 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
NACKF Flag (NACK Detection Flag)
[Setting condition]
• When ACK is not received (NACK is received) from the receiver in transmit mode with the ICFER.NACKE bit set
to 1 (transfer suspension enabled)
[Clearing conditions]
• When 0 is written to the NACKF bit after reading NACKF = 1
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
Note: When the NACKF flag is set to 1, the RIIC suspends data transmission/reception. Writing to the ICDRT register in
transmit mode or reading from the ICDRR register in receive mode with the NACKF flag set to 1 does not enable
data transmit/receive operation. To restart data transmission/reception, set the NACKF flag to 0.
RDRF Flag (Receive Data Full Flag)
[Setting conditions]
• When receive data has been transferred from the ICDRS register to the ICDRR register
This flag is set to 1 at the rising edge of the eighth or ninth SCL (selected by the ICMR3.RDRFS bit)
• When the received slave address matches after a start condition (or a restart condition) is detected with the
ICCR2.TRS bit set to 0
[Clearing conditions]
• When 0 is written to the RDRF bit after reading RDRF = 1
• When data is read from the ICDRR register
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
TEND Flag (Transmit End Flag)
[Setting condition]
• At the rising edge of the ninth SCL while the TDRE flag is 1
[Clearing conditions]
• When 0 is written to the TEND bit after reading TEND = 1
• When data is written to the ICDRT register
• When a stop condition is detected
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
TDRE Flag (Transmit Data Empty Flag)
[Setting conditions]
• When data has been transferred from the ICDRT register to the ICDRS register and the ICDRT register becomes
empty
• When the ICCR2.TRS bit is set to 1
• When the received slave address matches while the TRS bit is 1
[Clearing conditions]
• When data is written to the ICDRT register
• When the ICCR2.TRS bit is set to 0
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
Note: The NACKF flag becoming 1 while the ICFER.NACKE bit is 1 suspends data transmission and reception by the
RIIC. Even if the next data for transmission has already been written to the ICDRT register (the TDRE flag is 0),
the data in the ICDRT register is retained but not transferred to the ICDRS register. At this point, the TDRE flag
does not become 1.