Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1153 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.3 Operation
35.3.1 Communication Data Format
The I
2
C-bus format consists of 8-bit data and 1-bit acknowledgment. The first byte following a start condition or restart
condition is an address byte used to specify a slave device with which the master device communicates. The specified
slave is valid until a new slave is specified or a stop condition is generated.
Figure 35.3 shows the I
2
C-bus format, and Figure 35.4 shows the I
2
C-bus timing.
Figure 35.3 I
2
C-bus Format
Figure 35.4 I
2
C-bus Timing (SLA = 7 Bits)
S: Start condition. The master device drives the SDA0 line low from high while the SCL0 line is high.
SLA: Slave address, by which the master device selects a slave device.
R/W#: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to
the slave device when R/W is 0.
A: Acknowledge. The receiver drives the SDA0 line low. (In master transmit mode, the slave device returns acknowledge. In
master receive mode, the master device returns acknowledge.)
A#: Not Acknowledge. The receiver drives the SDA0 line high.
Sr: Restart condition. The master device drives the SDA0 line low from high after the setup time has elapsed with the SCL0 line
high.
DATA: Transmitted or received data
P: Stop condition. The master device drives the SDA0 line high from low while the SCL0 line is high.
[7-bit address format]
S R/W# A A A/A# P
S
SLA (7 bits)
W# A A A/A# PSLA (8 bits)11110b+SLA(2 bits)
DATA (8 bits)
A
S W# A A A/A# PSLA (8 bits)11110b+SLA(2 bits) ASr 11110b+SLA(2 bits) R
DATA (8 bits)
1 7 11 1 118
ADATA (8 bits)
1 7 11 1 118
1118
18
1 7 11 181 17 1
[10-bit address format]
n (n = 1 or more)
n (n = 1 or more)
n (n = 1 or more)
n: Number of transmit DATA bytes
1 to 7 8 9 1 to 7 8 9 1 to 7 8 9
S
SLA
R/W# A Data A
Data
AP
SCL0
SDA0