Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1014 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.2.19 SPI Mode Register (SPMR)
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR register are 0 (both serial transmission and reception
are disabled).
Note 2. Only 0 can be written to these bits, which clears the flag.
SPMR is used to select the extension settings in asynchronous and clock synchronous modes.
SSE Bit (SSn# Pin Function Enable)
Set this bit to 1 if the SSn# pin is to be used in control of transmission and reception (in simple SPI mode). Set this bit to
0 in any other mode. Furthermore, even for usage in simple SPI mode, the SSn# pin on the master side is not required to
control reception and transmission when master mode (SCR.CKE[1:0] = 00b and MSS = 0) is selected and there is a
single master, so the setting for the SSE bit is 0. Do not set both the SSE and CTSE bits to enabled (even if this setting is
made, operation is the same as that when these bits are set to 0).
CTSE Bit (CTS Enable)
Set this bit to 1 if the SSn# pin is to be used for inputting of the CTS control signal to control of transmission and
reception. The RTS signal is output when this bit is set to 0. Set this bit to 0 in smart card interface mode, simple SPI
mode, and simple I
2
C mode. Do not set both the CTSE and SSE bits to enabled (even if this setting is made, operation is
the same as that when these bits are set to 0).
MSS Bit (Master Slave Select)
This bit selects between master and slave operation in simple SPI mode. When the MSS bit is set to 1, data is received
through the SMOSIn pin and transmitted through the SMISOn pin.
Set this bit to 0 in modes other than simple SPI mode.
Address(es): SCI1.SPMR 0008 A02Dh, SCI5.SPMR 0008 A0ADh, SCI8.SPMR 0008 A10Dh, SCI12.SPMR 0008 B30Dh
b7 b6 b5 b4 b3 b2 b1 b0
CKPH CKPOL — MFF — MSS CTSE SSE
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 SSE SSn# Pin Function Enable 0: SSn# pin function is disabled.
1: SSn# pin function is enabled.
R/W*
1
b1 CTSE CTS Enable 0: CTS function is disabled (RTS output function is enabled).
1: CTS function is enabled.
R/W*
1
b2 MSS Master Slave Select 0: Transmission is through the SMOSIn pin and reception is
through the SMISOn pin (master mode).
1: Reception is through the SMOSIn pin and transmission is
through the SMISOn pin (slave mode).
R/W*
1
b3 — Reserved This bit is read as 0. The write value should be 0. R/W
b4 MFF Mode Fault Flag 0: No mode fault error
1: Mode fault error
R/W*
2
b5 — Reserved This bit is read as 0. The write value should be 0. R/W
b6 CKPOL Clock Polarity Select 0: Clock polarity is not inverted.
1: Clock polarity is inverted.
R/W*
1
b7 CKPH Clock Phase Select 0: Clock is not delayed.
1: Clock is delayed.
R/W*
1