Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1159 of 1852
Nov 30, 2020
RX23W Group 35. I
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C-bus Interface (RIICa)
Because the ICSR2.NACKF flag being 1 at this time indicates that no slave device recognized the address or there
was an error in communications, write 1 to the ICCR2.SP bit to generate a stop condition.
For master reception from a device with a 10-bit address, start by using master transmission to send the 10-bit
address, and then generate a restart condition. After that, transmitting 1111 0b, the two higher-order bits of the slave
address, and the R bit places the RIIC in master receive mode.
(4) Dummy read the ICDRR register after confirming that the ICSR2.RDRF flag is 1; this makes the RIIC start output
of the SCL and start data reception.
(5) After 1 byte of data has been received, the ICSR2.RDRF flag is set to 1 on the rising edge of the eighth or ninth SCL
(the clock signal) as selected by the ICMR3.RDRFS bit. Reading the ICDRR register at this time will produce the
received data, and the RDRF flag is automatically set to 0 at the same time. Furthermore, the value of the
acknowledgment bit received during the ninth SCL is returned as the value set in the ICMR3.ACKBT bit.
Furthermore, if the next byte to be received is the next to last byte, set the ICMR3.WAIT bit to 1 (for wait insertion)
before reading the ICDRR register (containing the second byte from last). As well as enabling NACK output even
in the case of delays in processing to set the ICMR3.ACKBT bit to 1 (NACK) in step (6), due to other interrupts,
etc., this fixes the SCL0 line to low on the falling edge of the ninth clock pulse in reception of the last byte, so the
state is such that generating a stop condition is possible.
(6) When the ICMR3.RDRFS bit is 0 and the slave device must be notified that it is to end transfer for data reception
after transfer of the next (final) byte, set the ICMR3.ACKBT bit to 1 (NACK).
(7) After reading the byte before last from the ICDRR register, if the value of the ICSR2.RDRF flag is confirmed to be
1, write 1 to the ICCR2.SP bit (requests to generate a stop condition) and then read the last byte from the ICDRR
register. When the ICDRR register is read, the RIIC is released from the wait state and generates the stop condition
after low-level output in the ninth clock pulse is completed or the SCL0 line is released from the low-hold state.
(8) Upon detecting the stop condition, the RIIC automatically sets bits MST and TRS in the ICCR2 register to 00b and
enters slave receive mode. Furthermore, detection of the stop condition leads to setting of the ICSR2.STOP flag to
1.
(9) After checking that the ICSR2.STOP flag is 1, set the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.