Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1161 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
Figure 35.11 Example of Master Reception (7-Bit Address Format, 3 Bytes or More)
[3] Transmit the slave address followed by R and
check ACK.
No
Yes
[2] Check I
2
C-bus occupation and generate a
start condition.
Yes
Yes
Master reception
ICCR2.ST = 1
Initial settings
No
Yes
Write data to ICDRT register
Yes
No
ICSR2.NACKF = 0?
Yes
Perform dummy read of ICDRR
register
ICSR2.RDRF = 1?
Yes
Next data = Final byte - 1?
No
Read ICDRR register
Set ICMR3.ACKBT bit
Read ICDRR register
No
No
ICSR2.STOP = 0
ICCR2.SP = 1
Read ICDRR register
ICMR3.WAIT = 0
ICSR2.STOP = 0
ICCR2.SP = 1
Perform dummy read of ICDRR
register
ICSR2.STOP = 1?
No
End of master reception
ICSR2.NACKF = 0
ICSR2.STOP = 0
Yes
[1] Initial settings
[4] Perform dummy read.
[5] Read received data and prepare for receiving
final data.
[6] Set the acknowledgment and read data
of (final byte – 1 byte).
[7] Read final data and generate a stop
condition.
[8] Check stop condition generation
[9] Processing for the next transfer operation
No
ICSR2.TDRE = 1?
ICSR2.RDRF = 1?
ICSR2.RDRF = 1?
ICCR2.BBSY = 0?
Next data = Final byte - 2?
ICMR3.WAIT = 1
No
Yes