Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1163 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
Figure 35.14 Master Receive Operation Timing (3) (When RDRFS bit is 0)
9
TDRE
MST
TRS
BBSY
TEND
STOP
ICDRT
ICDRS
2
b6
4
b4
5
b3
6
b2
7
b1
3
b5
8
b0
8
b0
1
b7
7
b1
DATA n-2
SP
DATA n-2
RDRF
ICDRR
DATA n-3
WAIT
ACKBT
ACKBR
[5]
9
DATA n-1
DATA n-1
DATA n-2
0 (ACK)0 (ACK)
0 (ACK)
Write 1 to
WAIT bit
Read ICDRR
register (DATA n-2)
ACK
ACK
XXXX (last data for transmission
[7-bit addresses + R/Upper 10 bits + R])
Receive data (DATA n-2)
Clear
STOP flag
DATA n-1
Automatic low hold (WAIT)
Read ICDRR register
(last data for reception
[DATA n])
0 (ACK)
DATA n
DATA n
1 2
b6
4
b4
5
b3
6
b2
7
b1
3
b5
8
b0
DATA n
9
NACK
[6] [7]
P
[9]
1 (NACK)
1 (NACK)
Set WAIT
bit to 0
Write 1
to SP bit
Write 1 to
ACKBT bit
Read ICDRR
register
(DATA n-1)
0
Receive data (DATA n)
b7
Automatic low hold (WAIT)
Receive data (DATA n-1)
SCL0
SDA0