Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1169 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.4 SCL Synchronization Circuit
In generation of the SCL, the RIIC starts counting out the value for width at high level specified in the ICBRH register
when it detects a rising edge on the SCL0 line and drives the SCL0 line low once counting of the width at high level is
complete. When the RIIC detects the falling edge of the SCL0 line, it starts counting out the width at low period
specified in the ICBRL register, and then stops driving the SCL0 line (releases the line) once counting of the width at low
level is complete. The SCL is thus generated.
If multiple master devices are connected to the I
2
C-bus, a collision of SCL signals may arise due to contention with
another master device. In such cases, the master devices have to synchronize their SCL signals. Since synchronization of
the SCL signals must be handled bit by bit, the RIIC is equipped with a facility (the SCL synchronization circuit) for
obtaining bit-by-bit synchronization of the SCL signals by monitoring the SCL0 line while in master mode.
When the RIIC has detected a rising edge on the SCL0 line and thus started counting out the width at high level specified
in the ICBRH register, and the level on the SCL0 line falls because an SCL signal is being generated by another master
device, the RIIC stops counting when it detects the falling edge, drives the level on the SCL0 line low, and starts
counting out the width at low level specified in the ICBRL register. When the RIIC finishes counting out the width at low
level, it stops driving the SCL0 line low (i.e. releases the line). At this time, if the width at low level of the SCL signal
from the other master device is longer than the width at low level set in the RIIC, the width at low level of the SCL signal
will be extended. Once the width at low level for the other master device has ended, the SCL signal rises because the
SCL0 line has been released. When the RIIC finishes outputting the low period of the SCL, the SCL0 line is released and
the SCL rises. That is, in cases of contention of SCL signals from more than one master, the width at high level of the
SCL signal is synchronized with that of the clock having the narrower width, and the width at low level of the SCL signal
is synchronized with that of the clock having the broader width. However, such synchronization of the SCL signal is only
enabled when the ICFER.SCLE bit is set to 1.
Figure 35.21 Generation and Synchronization of the SCL Signal from the RIIC
ICBRH
ICBRL
ICBRL
ICBRH
ICBRH
ICBRL
[SCL generation]
Compare match
(Counter clear, low-drive start)
ICBRH
ICBRL
Counter clearCounter clear
ICBRH
ICBRH
ICBRL
ICBRH: I
2
C-bus bit rate high-level register (SCL high period counter)
ICBRL: I
2
C-bus bit rate low-level register (SCL low period counter)
[SCL synchronization]
Rising of SCL detected
(High period count start)
Low-level output of
other master device
Low-level output of
other master device
SCL0
SCL0
Falling of SCL0 detected
(Low period count start)
Compare match
(Counter clear, SCL0 line released)