Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1173 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
Figure 35.25 AASy Flag Set Timing with 10-Bit Address Format Selected
Figure 35.26 AASy Flag Set/Clear Timing with 7-Bit/10-Bit Address Formats Mixed
Read ICDRR register
(Dummy read [lower addresses])
Address match
TDRE
AASy
S
1
1
8
W
1
8
R
9
ACK
TRS
9
ACK
BBSY
TDRE
AASy
TRS
BBSY
RDRF
RDRF
234567 8 9
ACK
S
1 2345
Data
Address match
234567
1110
1
1
8
W
9
ACK
234567
1110
1
1
234567
1110
9
ACK
Sr1to8
[10-bit address format: Slave reception]
[10-bit address format: Slave transmission]
10-bit slave address (lower 8 bits)Upper 2 bits
Read ICDRR register
(Dummy read [lower addresses])
Receive data (lower addresses)
Upper 2 bits Lower 8 bits Upper 2 bits
Receive data (lower addresses)
SCL0
SDA0
SCL0
SDA0
Upper 2 bits
Address match
AAS1
AAS2
AAS0
BBSY
1 W11 10
Lower 8 bits
R/W
Address match
AAS1
AAS2
AAS0
BBSY
Address mismatchAddress match
WDATA 1 1110R/W
AAS1
AAS2
AAS0
BBSY
S
7-bit slave address (SARL0)
Address mismatch
Address match
DATAR/W 7-bit slave address (SARL1) R/W
Address match
Address mismatch
S 9Sr23456711
to
8 98345679812
S 9Sr23456711
to
8 9834567981
2
S 9Sr23456711
to
8 9834567981
2
7-bit slave address (SARL1)
Upper 2 bits
7-bit slave address (SARL0)
ACK
ACKACK
ACK
ACK
ACKACK
[In the case of SARL0: 7-bit address, SARL1: 7-bit address, SAR2: 10-bit address (2)]
[In the case of
SARL0: 7-bit address, SARL1: 7-bit address, SAR2: 10-bit address (3)]
[In the case of
SARL0: 7-bit address, SARL1: 7-bit address, SAR2: 10-bit address (1)]
ACKACK
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0