Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1017 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.2.23 Control Register 2 (CR2)
Address(es): SCI12.CR2 0008 B323h
b7 b6 b5 b4 b3 b2 b1 b0
RTS[1:0] BCCS[1:0] — DFCS[2:0]
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b2 to b0 DFCS[2:0] RXDX12 Signal Digital Filter
Clock Select
b2 b0
0 0 0: Filter is disabled.
0 0 1: Filter clock is base clock*
1,
*
2
0 1 0: Filter clock is PCLK/8
0 1 1: Filter clock is PCLK/16
1 0 0: Filter clock is PCLK/32
1 0 1: Filter clock is PCLK/64
1 1 0: Filter clock is PCLK/128
1 1 1: Setting prohibited
R/W
b3 — Reserved This bit is read as 0. The write value should be 0. R/W
b5, b4 BCCS[1:0] Bus Collision Detection Clock
Select
• When SEMR.BGDM = 0 or SEMR.BGDM = 1 and
SMR.CKS[1:0] = a value other than 00b
b5 b4
0 0: Base clock
0 1: Base clock frequency divided by 2
1 0: Base clock frequency divided by 4
1 1: Setting prohibited
• When SEMR.BGDM = 1 and SMR.CKS[1:0] = 00b
b5 b4
0 0: Base clock frequency divided by 2
0 1: Base clock frequency divided by 4
1 0: Setting prohibited
1 1: Setting prohibited
R/W
b7, b6 RTS[1:0] RXDX12 Reception Sampling
Timing Select
• When SCI12.SEMR.ABCS = 0
b7 b6
0 0: Rising edge of the 8th cycle of base clock
0 1: Rising edge of the 10th cycle of base clock
1 0: Rising edge of the 12th cycle of base clock
1 1: Rising edge of the 14th cycle of base clock
• When SCI12.SEMR.ABCS = 1
b7 b6
0 0: Rising edge of the 4th cycle of base clock
0 1: Rising edge of the 5th cycle of base clock
1 0: Rising edge of the 6th cycle of base clock
1 1: Rising edge of the 7th cycle of base clock
R/W
Note: The period of the base clock is 1/16 of a single bit period when the SCI12.SEMR.ABCS is 0, and 1/8 of a single bit period
when the SCI12.SEMR.ABCS is 1.
Note 1. To use the base clock, set the SCI12.SCR.TE bit to 1.
Note 2. The base clock divided by 2 is the filter clock when the SEMR.BGDM bit is 1 and the SMR.CKS[1:0] bits are 00b.