Users Manual

R01UH0823EJ0110 Rev.1.10 Page 1192 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.12 SMBus Operation
The RIIC is available for data communication conforming to the SMBus (Version 2.0). To perform SMBus
communication, set the ICMR3.SMBS bit to 1. To use the transfer rate within a range of 10 kbps to 100 kbps of the
SMBus specification, set the ICMR1.CKS[2:0] bits, the ICBRH register, and the ICBRL register. In addition, determine
the values of the ICMR2.DLCS bit and the ICMR2.SDDL[2:0] bits to meet the data hold time (300 ns (min.)). If the
RIIC is used only as a slave device, the transfer rate setting is not necessary, whereas the ICBRL register needs to be set
to a value longer than the data setup time (250 ns).
For the SMBus device default address (1100 001b), use one of the slave address registers L0 to L2 (registers SARL0,
SARL1, and SARL2), and set the corresponding SARUy.FS bit (7-bit/10-bit address format select) (y = 0 to 2) to 0 (7-bit
address format).
When transmitting the UDID (Unique Device Identifier), set the ICFER.SALE bit to 1 to enable the slave arbitration-lost
detection function.
35.12.1 SMBus Timeout Measurement
(1) Measuring timeout of slave device
The following period (timeout interval: T
LOW:SEXT
) must be measured for slave devices in SMBus communication.
• From start condition to stop condition
To measure timeout for slave devices, measure the period from start condition detection to stop condition detection with
the MTU or TMR timer using a start condition detection interrupt (STI) and stop condition detection interrupt (SPI) of
the RIIC. The measured timeout period must be within the cumulative clock low extend time (slave device) (T
LOW:SEXT
:
25 ms (max.)) of the SMBus specification.
If the time measured with the MTU or TMR exceeds the detect clock low timeout (T
TIMEOUT
: 25 ms (min.)) of the
SMBus specification, the slave device must release the bus by writing 1 to the ICCR1.IICRST bit to apply an internal
reset of the RIIC. When an internal reset is applied to the RIIC, it stops driving the SCL0 and SDA0 pins of the bus and
makes the SCL0/SDA0 pin outputs high-impedance, thus releasing the bus.
(2) Measuring timeout of master device
The following periods (timeout interval: T
LOW:MEXT
) must be measured for master devices in SMBus communication.
• From start condition to acknowledgment bit
• Between acknowledgment bits
• From acknowledgment bit to stop condition
To measure timeout for master devices, measure these periods with the MTU or TMR timer using a start condition
detection interrupt (STI), stop condition detection interrupt (SPI), and transmit end interrupt (TEI) or receive data full
interrupt (RXI) of the RIIC. The measured timeout period must be within the cumulative clock low extend time (master
device) (T
LOW:MEXT
: 10 ms (max.)) of the SMBus specification, and the total of all T
LOW:MEXT
from start condition to
stop condition must be within T
LOW:SEXT
: 25 ms (max.).
For the ACK receive timing (rising edge of the ninth SCL), monitor the ICSR2.TEND flag in master transmit mode
(master transmitter) and the ICSR2.RDRF flag in master receive mode (master receiver). For this reason, perform
bytewise transmit operation in master transmit mode, and hold the ICMR3.RDRFS bit 0 until the byte just before
reception of the final byte in master receive mode. While the RDRFS bit is 0, the RDRF flag is set to 1 at the rising edge
of the ninth SCL.
If the period measured with the MTU or TMR exceeds the cumulative clock low extend time (master device)
(T
LOW:MEXT
: 10 ms (max.)) of the SMBus specification or the total of measured periods exceeds the detect clock low
timeout (T
TIMEOUT
: 25 ms (min.)) of the SMBus specification, the master device must stop the transaction by generating
a stop condition. In master transmit mode, immediately stop the transmit operation (writing data to the ICDRT register).