Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1193 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
Figure 35.41 SMBus Timeout Measurement
35.12.2 Packet Error Code (PEC)
This MCU incorporates a CRC calculator. The CRC calculator enables transmission of a packet error code (PEC) or
checking the received data of the SMBus in data communication of the RIIC. For the CRC generating polynomials of the
CRC calculator, refer to
section 39, CRC Calculator (CRC).
The PEC data in master transmit mode can be generated by writing all transmit data to the CRC data input register
(CRCDIR) in the CRC calculator.
The PEC data in master receive mode can be checked by writing all receive data to CRCDIR in the CRC calculator and
comparing the obtained value in the CRC data output register (CRCDOR) with the received PEC data.
To send ACK or NACK according to the match or mismatch result when the final byte is received as a result of the PEC
code check, set the ICMR3.RDRFS bit to 1 before the rising edge of the eighth SCL during reception of the final byte,
and hold the SCL0 line low at the falling edge of the eighth clock pulse.
35.12.3 SMBus Host Notification Protocol (Notify ARP Master Command)
In communications over an SMBus, a slave device can temporarily act as a master device to notify the SMBus host (or
ARP master) of its own slave address or to request its own slave address from the SMBus host.
For a product of this MCU to operate as an SMBus host (or ARP master), the host address (0001 000b) sent from the
slave device must be detected as a slave address, so the RIIC has a function for detecting the host address. To detect the
host address as a slave address, set the ICMR3.SMBS bit and the ICSER.HOAE bit to 1. Operation after the host address
has been detected is the same as normal slave operation.
S 1 1
P
998
R/W
7
7-bit slave address
2
97
Data
2
872 8 72 87
Data
2
81
Start Stop
Clk
ACK
T
LOW:SEXT
Clk
ACK
T
LOW:MEXT
T
LOW:MEXT
Clk
ACK
T
LOW:MEXT
TEND
TDRE
BBSY
RDRF
START
STOP
RDRFS
T
LOW:MEXT
T
LOW:SEXT
: Cumulative clock low extend time (slave device)
T
LOW:MEXT
: Cumulative clock low extend time (master device)
SMBus specification
ACK ACK A/NA
SCL0
SDA0
Measured with the MTU or TMR