Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1194 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.13 Interrupt Sources
The RIIC generates four types of interrupt request: transfer error or event generation (arbitration-lost, NACK detection,
timeout detection, start condition detection, and stop condition detection), receive data full, transmit data empty, and
transmit end.
Table 35.6 lists details of the several interrupt requests. The receive data full and transmit data empty are both capable of
activating data transfer by the DTC or DMAC.
Table 35.6 Interrupt Sources
Note: There is a delay time between the execution of a write instruction for a peripheral module by the CPU and actual writing to the
module. Thus, when an interrupt flag has been cleared or an interrupt request has been masked, read the relevant flag again to
check whether clearing or masking has been completed, and then return from interrupt handling. Returning from interrupt
handling without checking that writing to the module has been completed creates a possibility of repeated processing of the
same interrupt.
Note 1. Because TXI is an edge-detected interrupted, it does not require clearing. Furthermore, the ICSR2.TDRE flag (a condition for
TXI) is automatically set to 0 when data for transmission are written to the ICDRT register or a stop condition is detected
(ICSR2.STOP flag is 1).
Note 2. Because RXI is an edge-detected interrupted, it does not require clearing. Furthermore, the ICSR2.RDRF flag (a condition for
RXI) is automatically set to 0 when data are read from the ICDRR register.
Note 3. When using the TEI interrupt, clear the ICSR2.TEND flag in the TEI interrupt handling.
Note that the ICSR2.TEND flag is automatically set to 0 when data for transmission are written to the ICDRT register or a stop
condition is detected (ICSR2.STOP flag is 1).
Clear the each flag or mask the interrupt request during interrupt handling.
35.13.1 Buffer Operation for TXI and RXI Interrupts
If the conditions for generating a TXI and RXI interrupt are satisfied while the corresponding IR flag is 1, the interrupt
request is not output for the ICU but retained internally (the capacity for internal retention is one request per source).
An interrupt request that was being retained internally is output to the ICU when the value of the ICU.IRn.IR flag
becomes 0. Internally retained interrupt requests are automatically cleared under normal conditions of usage.
Internally retained interrupt requests can also be cleared by writing 0 to the corresponding interrupt enable bit in the
ICIER register.
Symbol Interrupt Source Interrupt Flag
DTC
Activation
DMAC
Activation Interrupt Condition
EEI Transfer error/
event generation
AL Not possible Not possible AL = 1 and ALIE = 1
NACKF NACKF = 1 and NAKIE = 1
TMOF TMOF = 1 and TMOIE = 1
START START = 1 and STIE = 1
STOP STOP = 1 and SPIE = 1
RXI*
2
Receive data full RDRF Possible Possible RDRF = 1 and RIE = 1
TXI*
1
Transmit data empty TDRE Possible Possible TDRE = 1 and TIE = 1
TEI*
3
Transmit end TEND Not possible Not possible TEND = 1 and TEIE = 1