Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1000 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Table 33.16 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
PCLK (MHz) External Input Clock (MHz)
Maximum Bit Rate (bps)
SEMR.ABCS Bit = 0 SEMR.ABCS Bit = 1
8 2.0000 125000 250000
9.8304 2.4576 153600 307200
10 2.5000 156250 312500
12 3.0000 187500 375000
12.288 3.0720 192000 384000
14 3.5000 218750 437500
16 4.0000 250000 500000
17.2032 4.3008 268800 537600
18 4.5000 281250 562500
19.6608 4.9152 307200 614400
20 5.0000 312500 625000
25 6.2500 390625 781250
30 7.5000 468750 937500
Table 33.17 Maximum Bit Rate with TMR Clock Input (Asynchronous Mode)
PCLK (MHz) TMR Clock (MHz)
Maximum Bit Rate (bps)
SEMR.ABCS Bit = 0 SEMR.ABCS Bit = 1
8 4 250000 500000
9.8304 4.9152 307200 614400
10 5 312500 625000
12 6 375000 750000
12.288 6.144 384000 768000
14 7 437500 875000
16 8 500000 1000000
17.2032 8.6016 537600 1075200
18 9 562500 1125000
19.6608 9.8304 614400 1228800
20 10 625000 1250000
25 12.5 781250 1562500
30 15 937500 1875000