Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1018 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.2.24 Control Register 3 (CR3)
SDST Bit (Start Frame Detection Start)
Detection of a Start Frame begins when this bit is set to 1. The bit is read as 0.
33.2.25 Port Control Register (PCR)
SHARPS Bit (TXDX12/RXDX12 Pin Multiplexing Select)
When this bit is set to 1, the TXDX12 and RXDX12 signals are multiplexed on the same pin so that half-duplex
communications become possible.
Address(es): SCI12.CR3 0008 B324h
b7 b6 b5 b4 b3 b2 b1 b0
———————SDST
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 SDST Start Frame Detection Start 0: Detection of Start Frame is not performed.
1: Detection of Start Frame is performed.
R/W
b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W
Address(es): SCI12.PCR 0008 B325h
b7 b6 b5 b4 b3 b2 b1 b0
———
SHARP
S
——
RXDXP
S
TXDXP
S
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 TXDXPS TXDX12 Signal Polarity Select 0: The polarity of TXDX12 signal is not inverted for output.
1: The polarity of TXDX12 signal is inverted for output.
R/W
b1 RXDXPS RXDX12 Signal Polarity
Select
0: The polarity of RXDX12 signal is not inverted for input.
1: The polarity of RXDX12 signal is inverted for input.
R/W
b3, b2 — Reserved These bits are read as 0. The write value should be 0. R/W
b4 SHARPS TXDX12/RXDX12 Pin
Multiplexing Select
0: The TXDX12 and RXDX12 pins are independent.
1: The TXDX12 and RXDX12 signals are multiplexed on the same
pin.
R/W
b7 to b5 — Reserved These bits are read as 0. The write value should be 0. R/W