Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1033 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.3.7 Serial Data Transmission (Asynchronous Mode)
Figure 33.10 to Figure 33.12 show an example of the operation for serial transmission in asynchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI transfers data from the TDR register
*
1
to the TSR register when data is written to the TDR register*
1
in the
TXI interrupt handling routine. The TXI interrupt request at the beginning of transmission is generated when the
SCR.TE bit is set to 1 after the SCR.TIE bit is set to 1 or when these 2 bits are set to 1 simultaneously by a single
instruction.
2. Transmission starts after the SPMR.CTSE bit is set to 0 (CTS function is disabled) and a low level on the CTSn#
pin causes data transfer from the TDR register
*
1
to the TSR register. If the SCR.TIE bit is 1 at this time, a TXI
interrupt request is generated. Continuous transmission is obtainable by writing the next transmit data to the TDR
register
*
1
in the TXI interrupt handling routine before transmission of the current transmit data is completed. When
TEI interrupt requests are in use, set the SCR.TIE bit to 0 (a TXI interrupt request is disabled) and the SCR.TEIE bit
to 1 (a TEI interrupt request is enabled) after the last of the data to be transmitted are written to the TDR register
*
1,
*
2
from the handling routine for TXI requests.
3. Data is sent from the TXDn pin in the following order: start bit, transmit data, parity bit or multi-processor bit (may
be omitted depending on the format), and stop bit.
4. The SCI checks for updating of (writing to) the TDR register
*
3
at the time of stop bit output.
5. When the TDR register
*
3
is updated, setting of the SPMR.CTSE bit to 0 (CTS function is disabled) or a low level
input on the CTSn# pin cause the next transfer of the next transmit data from the TDR register
*
1
to the TSR register
and sending of the stop bit, after which serial transmission of the next frame starts.
6. If the TDR register
*
3
is not updated, the SCI sets the SSR.TEND flag to 1, sends the stop bit, and then outputs high
to put the line in the mark state. If the SCR.TEIE bit is 1 at this time, the SSR.TEND flag is set to 1 and a TEI
interrupt request is generated.
Note 1. Write data not to the TDR register but to the TDRH and TDRL registers when 9-bit data length is selected.
Note 2. Write data in the order from the TDRH register to the TDRL register when 9-bit data length is selected.
Note 3. The SCI checks for updating of the TDRL register only and does not check for updating of the TDRH register
when 9-bit data length is selected.
Figure 33.13 shows a sample flowchart for serial transmission in asynchronous mode.