Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1037 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.3.8 Serial Data Reception (Asynchronous Mode)
Figure 33.14 and Figure 33.15 show an example of the operation for serial data reception in asynchronous mode.
In serial data reception, the SCI operates as described below.
1. When the value of the SCR.RE bit becomes 1, the output signal on the RTSn# pin goes to the low level.
2. When the SCI monitors the communications line and detects a start bit, it performs internal synchronization, stores
receive data in the RSR register, and checks the parity bit and stop bit.
3. If an overrun error occurs, the SSR.ORER flag is set to 1. If the SCR.RIE bit is 1 at this time, an ERI interrupt
request is generated. Receive data is not transferred to the RDR register
*
1
.
4. If a parity error is detected, the SSR.PER flag is set to 1 and receive data is transferred to the RDR register
*
1
. If the
SCR.RIE bit is 1 at this time, an ERI interrupt request is generated.
5. If a framing error (when the stop bit is 0) is detected, the SSR.FER flag is set to 1 and receive data is transferred to
the RDR register
*
1
. If the SCR.RIE bit is 1 at this time, an ERI interrupt request is generated.
6. When reception finishes successfully, receive data is transferred to the RDR register
*
1
. If the SCR.RIE bit is 1 at
this time, an RXI interrupt request is generated. Continuous reception is enabled by reading the receive data
transferred to the RDR register
*
1
in this RXI interrupt handling routine before reception of the next receive data is
completed. Reading the received data that have been transferred to the RDR register
*
1
causes the RTSn# pin to
output the low level.
Note 1. Read data not in the RDR register but in the RDRH and RDRL registers when 9-bit data length is selected.
Note 2. The SCI checks for reading of the RDRL register only and does not check for reading of the RDRH register when
9-bit data length is selected.
Figure 33.14 Example of SCI Operation for Serial Reception in Asynchronous Mode (1) (When RTS Function is
Not Used) (Example with 8-Bit Data, Parity, 1 Stop Bit)
RXI interrupt flag
(IRn in ICU*
1
)
SSR.FER flag
0
1 frame
D0 D1
D7 0/1 1 0 D0 D1 D7
0/1 0
Data Data
Parity
bit
Stop
bit
Start bit
Parity
bit
Stop
bit
Start bit
Idle state
(mark state)
ERI interrupt request generated
by framing error
RXI interrupt
request
generated
RDR data read in RXI interrupt
handling routine
Note 1. Refer to section 15, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.