Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1042 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.4.1 Multi-Processor Serial Data Transmission
Figure 33.19 is a sample flowchart of multi-processor data transmission. In the ID transmission cycle, the ID should be
transmitted with the SSR.MPBT bit set to 1. In the data transmission cycle, the data should be transmitted with the
MPBT bit set to 0. The other operations are the same as the operations in asynchronous mode.
Figure 33.19 Example of Multi-Processor Serial Transmission Flowchart
No
End
Yes
Initialization
Start data transmission
Set the SSR.MPBT bit
No
Yes
No
Yes
Set the SCR.TIE bit to 0, and
set the SCR.TEIE bit to 1
No
Yes
Set the I/O port functions
Set the SCR.TE, TIE, and TEIE bits to 0
TXI interrupt
All data written?
TEI interrupt
Break output
Write transmit data to the TDR register
[ 3 ]
[ 1 ]
[ 4 ]
[ 2 ]
Note: The TDR register becomes the TDRH and TDRL
registers when 9-bit data length is selected. Write
data in the order from the TDRH register to the
TDRL register.
[ 1 ] SCI initialization:
Set data transmission.
After the SCR.TE bit is set to 1, high is output for a
frame, and transmission is enabled.
[ 2 ] TXI interrupt request:
When transmit data is transferred from the TDR register
to the TSR register, a transmit data empty interrupt
(TXI) request is generated.
Set the SSR.MPBT bit to 0 or 1, and write transmit data
to the TDR register once in the TXI interrupt handling
routine.
[ 3 ] Serial transmission continuation procedure:
To continue serial transmission, write transmit data to
the TDR register once using a TXI interrupt request.
Transmit data can also be written to the TDR register
by activating the DMAC or DTC.
When TEI interrupt requests are in use, set the
SCR.TIE bit to 0 and the SCR.TEIE bit to 1 after the last
of the data to be transmitted are written to the TDR
register.
[ 4 ] Break output at the end of serial transmission:
To output a break in serial transmission, set the I/O port
function corresponding to the TXDn pin (corresponding
to output of the low level), and after switching the TXDn
pin to the general I/O port function, set the SCR.TE bit
to 0.