Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1069 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.7 Operation in Simple I
2
C Mode
Simple I
2
C-bus format is composed of 8 data bits and an acknowledge bit. By continuing into a slave-address frame after
a start condition or restart condition, a master device is able to specify a slave device as the partner for communications.
The currently specified slave device remains valid until a new slave device is specified or a stop condition is satisfied.
The 8 data bits in all frames are transmitted in order from the MSB.
The I
2
C-bus format and timing of the I
2
C-bus are shown in Figure 33.46 and Figure 33.47.
Figure 33.46 I
2
C-bus Format
Figure 33.47 I
2
C-bus Timing (When SLA is 7 Bits)
S: Indicates a start condition, i.e. the master device changing the level on the SSDAn line from the high to the low level while
the SSCLn line is at the high level.
SLA: Indicates a slave address, by which the master device selects a slave device.
R/W#: Indicates the direction of transfer (reception or transmission). The value 1 corresponds to transfer from the slave device
to the master device and 0 corresponds to transfer from the master device to the slave device.
A/A#: Indicates an acknowledge bit. This is returned by the slave device for master transmission and by the master device for
master reception. Return of the low level indicates ACK and return of the high level indicates NACK.
Sr: Indicates a restart condition, i.e. the master device changing the level on the SSDAn line from the high to the low level
while the SSCLn line is at the high level and after the setup time has elapsed.
DATA: Indicates the data being received or transmitted.
P: Indicates a stop condition, i.e. the master device changing the level on the SSDAn line from the low to the high level while
the SSCLn line is at the high level.
7-bit address format reception
S SLA (7 bits) R A DATA (8 bits) A A# P
1 1 1 1 1 17 8
n (n = 1 or larger)
n: Number of transfer frames
10-bit address format transmission
S
11110b + SLA
(2 bits)
W# ASLA (8 bits)
1 1 17 8
ADATA (8 bits)A A/A# P
1 1 1 18
n (n = 1 or larger)
S
11110b + SLA
(2 bits)
W# ASLA (8 bits)
1 1 17 8
A
DATA (8 bits)
A A# P
1 1 1 18
n (n = 1 or larger)
Sr
11110b + SLA
(2 bits)
RA
1 1 17
10-bit address format reception
7-bit address format transmission
S SLA (7 bits) W# A DATA (8 bits) A A/A# P
1 1 1 1 1 17 8
n (n = 1 or larger)
: Master device → Slave device
: Slave device → Master device
SSDAn
SSCLn 1-7 8 9
1-7 8 9
SSLAR/W#A
DATA A
DATA
A
P
1-7 8 9
D7-D1 D0 D7-D1 D0 D7-D1 D0
MSB LSB