Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1070 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.7.1 Generation of Start, Restart, and Stop Conditions
Writing 1 to the SIMR3.IICSTAREQ bit causes the generation of a start condition. The generation of a start condition
proceeds through the following operations.
• The level on the SSDAn line falls (from the high level to the low level) and the SSCLn line is kept in the released
state.
• The hold time for the start condition is secured as half of a bit period at the bit rate determined by the setting of the
BRR.
• The level on the SSCLn line falls (from the high level to the low level), the SIMR3.IICSTAREQ bit is set (to 0), and
a start-condition generated interrupt is output.
Writing 1 to the SIMR3.IICRSTAREQ bit causes the generation of a start condition. The generation of a start condition
proceeds through the following operations.
• The SSDAn line is released and the SSCLn line is kept at the low level.
• The period at low level for the SSCLn line is secured as half of a bit period at the bit rate determined by the setting
of the BRR.
• The SSCLn line is released (transition from the low to the high level).
• Once the high level on the SSCLn line is detected, the setup time for the restart condition is secured as half of a bit
period at the bit rate determined by the setting of the BRR.
• The level on the SSDAn line falls (from the high level to the low level).
• The hold time for the restart condition is secured as half of a bit period at the bit rate determined by the setting of the
BRR.
• The level on the SSCLn line falls (from the high level to the low level), the SIMR3.IICRSTAREQ bit is set (to 0),
and a restart-condition generated interrupt is output.
Writing 1 to the SIMR3.IICSTPREQ bit causes the generation of a stop condition. The generation of a stop condition
proceeds through the following operations.
• The level on the SSDAn line falls (from the high level to the low level) and the SSCLn line is kept at the low level.
• The period at low level for the SSCLn line is secured as half of a bit period at the bit rate determined by the setting
of the BRR.
• The SSCLn line is released (transition from the low to the high level).
• Once the high level on the SSCLn line is detected, the setup time for the stop condition is secured as half of a bit
period at the bit rate determined by the setting of the BRR.
• The SSDAn is released (transition from the low to the high level), the SIMR3.IICSTPREQ bit is set (to 0), and a
stop-condition generated interrupt is output.