Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1072 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.7.2 Clock Synchronization
The SSCLn line may be placed at the low level in the case of a wait inserted by a slave device as the other side of
transfer. Setting the SIMR2.IICCSC bit to 1 applies control to obtain synchronization when the levels of the internal
SSCLn clock signal and the level being input on the SSCLn pin differ.
When the SIMR2.IICCSC bit is set to 1, the level of the internal SSCLn clock signal changes from low to high, counting
to determine the period at high level is stopped while the low level is being input on the SSCLn pin, and counting to
determine the period at high level starts after the transition of the input on the SSCLn pin to the high level. The interval
from this time until counting to determine the period at high level starts on the transition of the SSCLn pin to the high
level is the total of the delay of SSCLn output, delay for noise filtering of the input on the SSCLn pin (2 or 3 cycles of
sampling clock for the noise filter), and delay for internal processing (1 or 2 cycles of PCLK). The period at high level of
the internal SSCLn clock is extended even if other devices are not placing the low level on the SSCLn line. If the
SIMR2.IICCSC bit is 1, synchronization is obtained for the transmission and reception of data by taking the logical AND
of the input on the SSCLn pin and the internal SSCLn clock. If the SIMR2.IICCSC bit is 0, synchronization with the
internal SSCLn clock is obtained for the transmission and reception of data.
If a slave device inserts a period of waiting into the interval until the transition of the internal SSCLn clock signal from
the low to the high level after a request for the generation of a start, restart, or stop condition is issued, the time until
generation is prolonged by that period.
If a slave device inserts a period of waiting after the transition of the internal SSCLn clock signal from the low to the
high level, although the generation-completed interrupt is issued without stopping the period of waiting, generation of
the condition itself is not guaranteed.
Figure 33.49 shows an example of operations to synchronize the clocks.
Figure 33.49 Example of Operations for Clock Synchronization
SSCLn output from the
other device
SSCLn line
Internal SSCLn clock
Counting is stopped while the
SSCLn line is at the low level.
Counting of the period
at high level starts.
Clock driving transfer
internally
Counting of the period
at high level starts.
Counting is stopped until the SSCLn
line being at the high level is
conveyed within the SCI.
Counting of the period
at low level starts.