Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1074 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.7.4 SCI Initialization (Simple I
2
C Mode)
Before transferring data, write the initial value (00h) to the SCR register and initialize the interface following the
example shown in
Figure 33.51.
When changing the operating mode, transfer format, and so on, be sure to set the SCR register to its initial value before
proceeding with the changes.
In simple I
2
C mode, the open-drain setting for the communication ports should be made on the port side.
Figure 33.51 Example of the Flowchart of SCI Initialization (for Simple I
2
C Mode)
Start of transmission or reception
Set up the transfer or reception format in
the SMR and SCMR registers
Set the values in the SEMR, SNFR,
SIMR1, SIMR2, and SPMR registers
Set the SCR.TIE, RIE, TE, RE, TEIE and
CKE[1:0] bits to 0
Set the I/O port functions
Set the SCR.RE and TE bit to 1 and set
the SCR.TIE, RIE and TEIE bits
Set the SIMR3.IICSDAS[1:0] and
IICSCLS[1:0] bits to 11b
[ 1 ]
[ 2 ]
[ 3 ]
[ 6 ]
[ 7 ]
[ 1 ] Make I/O port settings that allow use (on N-channel open-drain
output pins) of the SSCLn and SSDAn pin functions.
[ 2 ] Place the SSCLn and SSDAn pins in the high-impedance state
until a start condition is to be generated.
[ 3 ] Set the format for transmission and reception in the SMR and
SCMR registers.
In the SMR register, set the CKS[1:0] bits to the desired value
and set the other bits to 0.
In the SCMR register, set the SDIR bit to 1 and the SINV and
SMIF bits to 0.
[ 4 ] Write the value for the desired bit rate to the BRR register.
[ 5 ] Write the value obtained by correcting a bit rate error in the
MDDR register. This step is not necessary if the SEMR.BRME
bit is set to 0.
[ 6 ] Set the values in the SEMR, SNFR, SIMR1, SIMR2, and SPMR
registers.
In the SEMR register, set the NFEN and BRME bits.
In the SNFR register, set the NFCS[2:0] bits.
In the SIMR1 register, set the IICM bit to 1 and the IICDL[4:0]
bits as required.
In the SIMR2 register, set the IICACKT and IICCSC bits to 1
and the IICINTM bits as required.
In the SPMR register, set all the bits to 0.
[ 7 ] Set the SCR.RE and TE bits to 1. At this time, also set the
SCR.TIE, RIE, and TEIE bits (for transmission and when the
SIMR2.IICINTM bit is 1, set the RIE bit to 0).
Setting the TE and RE bits to 1 makes the SSCLn and SSDAn
pin functions available.
Set the value in the BRR register
[ 4 ]
Set a value in the MDDR register
[ 5 ]
Start of initialization
Note: Set the SCR.RE and TE bits to 0 or 1 at the same time.