Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1080 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.8 Operation in Simple SPI Mode
As an extended function, the SCI supports a simple SPI mode that handles transfer among one or multiple master devices
and multiple slave devices.
Making the settings for clock synchronous mode (SCMR.SMIF = 0, SIMR1.IICM = 0, SMR.CM = 1) plus setting the
SPMR.SSE bit to 1 places the SCI in simple SPI mode. However, the SS pin function on the master side is unnecessary
for connection of the device used as the master in simple SPI mode when the configuration only has a single master, so
set the SPMR.SSE bit to 0 in such cases.
Figure 33.57 shows an example of connections for simple SPI mode. Control a general port pin to produce the SS
output signal from the master.
In simple SPI mode, data are transferred in synchronization with clock pulses in the same way as in clock synchronous
mode. One character of data for transfer consists of 8 bits of data, and parity bits cannot be appended to this. The data can
be inverted by setting the SCMR.SINV bit to 1.
Since the receiver and transmitter are independent of each other within the SCI module, full-duplex communications are
possible, with a common clock signal. Furthermore, since both the transmitter and receiver have a double-buffered
structure, writing of further transmit data while transmission is in progress and reading of previously received data while
reception is in progress are both possible. Continuous transfer is thus possible.
Figure 33.57 Example of Connections via a Simple SPI Mode (In Single Master Mode, SPMR.SSE Bit = 0)
SMOSIn (output)
SMISOn (input)
Device 1 (master)
SCKn (output)
Port pin (output)
SSn# (input)
Port pin (output)
SMOSIn (input)
SMISOn (output)
Device 2 (slave)
SCKn (input)
SSn# (input)
SMOSIn (input)
SMISOn (output)
Device 3 (slave)
SCKn (input)
SSn# (input)
*
1
Note 1. The SSn# input is not required in a single-master system
(the interface is used with the setting SPMR.SSE = 0).