Users Manual

R01UH0823EJ0110 Rev.1.10 Page 1083 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.8.5 SCI Initialization (Simple SPI Mode)
The procedure is the same as for initialization in clock synchronous mode Figure 33.24, Sample SCI Initialization
Flowchart. The CKPOL and CKPH bits in the SPMR register must be set to ensure that the kind of clock signal they
select is suitable for both master and slave devices.
For initialization, changes to the operating mode, changes to the transfer format, and so on, initialize the SCR register
before proceeding with changes.
As well as setting the RE bit to 0, note that the SSR.ORER, FER, and PER flags, as well as the RDR register, are not
initialized.
33.8.6 Transmission and Reception of Serial Data (Simple SPI Mode)
In master operation, ensure that the SSn# pin of the slave device on the other side of the transfer is at the low level before
starting the transfer and at the high level on completion of the transfer. Otherwise, the procedures are the same as in clock
synchronous mode.
33.9 Bit Rate Modulation Function
The bit rate modulation function corrects the bit rate by thinning out the specified amount of clocks from those input to
the baud rate generator.
When the SEMR.BRME bit is 1, the baud rate generator validates and counts the average interval of the number of
clocks set in the MDDR register out of the total 256 clocks input.
Figure 33.59 assumes the SCI is in asynchronous mode, bits SMR.CKS[1:0] are 00b, the BRR register is 00h, and the
MDDR register is 160. In this example, the cycle of the base clock is evenly corrected to 256/160, and the bit rate is
corrected to 160/256. Note that there is an imbalance in thinning out the internal clock, and expansion and contraction
occur in the pulse width of the base clock.
Note: Do not use this function in clock synchronous mode and in the highest speed settings in simple SPI mode
(SMR.CKS[1:0] = 00b, SCR.CKE[1] = 0, and BRR = 0).
Figure 33.59 Example of the Base Clock When the Bit Rate Modulation Function is Used
The input of a clock signal with a shorter period to the baud rate generator reduces difference in the generated base clock
period and, since the division ratio of the baud rate generator also becomes larger, reduces difference in the length of the
1-bit period.
Transmit data/receive data
Base clock
Internal clock
(bit rate counter input)
(1) Example when not using bit rate modulation
96 out of 256 clocks are disabled by the MDDR register setting (160 clocks are enabled)
1-bit period is 16 cycles of the base clockTransmit data/receive data
Base clock
Internal clock
(bit rate counter input)
This bit extends the 1-bit period to (average 1-bit period is corrected to )
1-bit period is 16 cycles of the base clock
(2) Example when using bit rate modulation, and corrected to
160
256
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515212
1234567
89 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2
52
32
256
160