Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1086 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.62 Example of Start Frame Transmission (1/2)
Start
Set 1 to ESMER.ESME
Set CR2.RTS[1:0], BCCS[1:0], and
DFCS[2:0]
Set PCR.SHARPS, RXDXPS, and
TXDXPS
SCI12 initialization
Set 1 to each bit in STCR
Set ICR.AEDIE, BCDIE, PIBDIE,
CF1MIE, CF0MIE, and BFDIE
Set TMR.TCSS[2:0]
Set TCNT and TPRE
Set 10b to TMR.TOMS[1:0]
Enable the extended serial mode control section.
Set the timing of sampling for RXDX12 reception, clock for bus collision detection,
and sampling clock for the RXDX12 signal’s digital filter.
Set the RXDX12 and TXDX12 pins.
Set Break Field low width output mode as the operating mode of the timer.
Set the clock source for counting and registers TCNT and TPRE to values that suit
the period for the Break Field low width.
Initialize SCI12 (refer to the example of a flowchart of SCI initialization
(asynchronous mode). However, set the SCR.TE bit to 1 and the SCR.RE bit to 0
for transmission and the SCR.TE bit to 0 and the SCR.RE bit to 1 for reception.
Data for output need not be set at this stage.
Clear all flags in the STR register.
Set interrupt-enable bits as required.
A